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[/] [pci/] [tags/] [rel_9/] [bench/] [verilog/] [pci_unsupported_commands_master.v] - Diff between revs 89 and 92
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| Rev 89 |
Rev 92 |
| Line 279... |
Line 279... |
begin
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begin
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PAR_int <= #6 ^{AD, CBE, make_addr_parity_error} ;
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PAR_int <= #6 ^{AD, CBE, make_addr_parity_error} ;
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PAR_en <= #6 1'b1 ;
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PAR_en <= #6 1'b1 ;
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IRDY_en <= #6 1'b1 ;
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IRDY_en <= #6 1'b1 ;
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IRDY_int <= #6 1'b0 ;
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IRDY_int <= #6 1'b0 ;
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CBE_int <= #6 be ;
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CBE_int <= #6 ~be ;
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if (rw)
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if (rw)
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AD_int <= #6 data ;
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AD_int <= #6 data ;
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else
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else
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AD_en <= #6 1'b0 ;
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AD_en <= #6 1'b0 ;
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| Line 323... |
Line 323... |
PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
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PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
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AD_int <= #6 data ;
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AD_int <= #6 data ;
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end
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end
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IRDY_int <= #6 1'b0 ;
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IRDY_int <= #6 1'b0 ;
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CBE_int <= #6 be ;
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CBE_int <= #6 ~be ;
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@(posedge CLK);
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@(posedge CLK);
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get_termination(received_termination);
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get_termination(received_termination);
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end
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end
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endtask // subsequent_data_phase
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endtask // subsequent_data_phase
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| Line 344... |
Line 344... |
begin
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begin
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PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
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PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
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AD_int <= #6 data ;
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AD_int <= #6 data ;
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end
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end
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CBE_int <= #6 be ;
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CBE_int <= #6 ~be ;
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@(posedge CLK);
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@(posedge CLK);
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get_termination(received_termination);
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get_termination(received_termination);
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end
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end
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endtask // subsequent_data_phase
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endtask // subsequent_data_phase
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