| Line 37... |
Line 37... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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|
// Revision 1.11 2002/10/11 12:03:12 mihad
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|
// The testcase I just added in previous revision repaired
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//
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// Revision 1.10 2002/10/11 10:08:57 mihad
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// Revision 1.10 2002/10/11 10:08:57 mihad
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// Added additional testcase and changed rst name in BIST to trst
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// Added additional testcase and changed rst name in BIST to trst
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//
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//
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// Revision 1.9 2002/10/08 17:17:02 mihad
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// Revision 1.9 2002/10/08 17:17:02 mihad
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// Added BIST signals for RAMs.
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// Added BIST signals for RAMs.
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| Line 143... |
Line 146... |
wire TAR2_IDSEL = AD[`TAR2_IDSEL_INDEX] ;
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wire TAR2_IDSEL = AD[`TAR2_IDSEL_INDEX] ;
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|
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wire reset_wb ; // reset to Wb devices
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wire reset_wb ; // reset to Wb devices
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|
|
`ifdef PCI_BIST
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`ifdef PCI_BIST
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wire SO ;
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wire scanb_so ;
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reg SI ;
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reg scanb_si ;
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wire trst = reset_wb ;
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reg scanb_rst ;
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reg shift_DR ;
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reg scanb_en ;
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reg capture_DR ;
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reg scanb_clk ;
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reg extest ;
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reg tck ;
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`endif
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`endif
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|
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`ifdef GUEST
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`ifdef GUEST
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wire RST = ~reset ;
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wire RST = ~reset ;
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assign reset_wb = RST_O ;
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assign reset_wb = RST_O ;
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| Line 215... |
Line 216... |
.RTY_I ( RTY_I ),
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.RTY_I ( RTY_I ),
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.ERR_I ( ERR_I )
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.ERR_I ( ERR_I )
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|
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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.trst (trst),
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// bist chain signals
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.SO (SO),
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.scanb_rst (scanb_rst),
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.SI (SI),
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.scanb_clk (scanb_clk),
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.shift_DR (shift_DR),
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.scanb_si (scanb_si),
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.capture_DR (capture_DR),
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.scanb_so (scanb_so),
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.extest (extest),
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.scanb_en (scanb_en)
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.tck (tck)
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`endif
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`endif
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) ;
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) ;
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|
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WB_MASTER_BEHAVIORAL wishbone_master
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WB_MASTER_BEHAVIORAL wishbone_master
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(
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(
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| Line 649... |
Line 649... |
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initial
|
initial
|
begin
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begin
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|
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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SI = 0 ;
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scanb_si = 0 ;
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shift_DR = 0 ;
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scanb_en = 0 ;
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capture_DR = 0 ;
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scanb_clk = 0 ;
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extest = 0 ;
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scanb_rst = 0 ;
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tck = 0 ;
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`endif
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`endif
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next_test_name[79:0] <= "Nowhere___";
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next_test_name[79:0] <= "Nowhere___";
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reset = 1'b1 ;
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reset = 1'b1 ;
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pci_clock = 1'b0 ;
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pci_clock = 1'b0 ;
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wb_clock = 1'b1 ;
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wb_clock = 1'b1 ;
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| Line 928... |
Line 927... |
`ifdef DISABLE_COMPLETION_EXPIRED_TESTS
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`ifdef DISABLE_COMPLETION_EXPIRED_TESTS
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`else
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`else
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master_completion_expiration ;
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master_completion_expiration ;
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`endif
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`endif
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|
|
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`ifdef PCI_CLOCK_FOLLOWS_WB_CLOCK
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master_special_corner_case_test ;
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`endif
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$display(" ") ;
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$display(" ") ;
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$display("WB slave images' tests finished!") ;
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$display("WB slave images' tests finished!") ;
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|
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$display("########################################################################") ;
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$display("########################################################################") ;
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$display("########################################################################") ;
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$display("########################################################################") ;
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| Line 1199... |
Line 1202... |
test_name = "WB IMAGE CONFIGURATION" ;
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test_name = "WB IMAGE CONFIGURATION" ;
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// enable master & target operation
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// enable master & target operation
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config_write( pci_ctrl_offset, 32'h0000_0007, 4'h1, ok) ;
|
config_write( pci_ctrl_offset, 32'h0000_0007, 4'h1, ok) ;
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if ( ok !== 1 )
|
if ( ok !== 1 )
|
begin
|
begin
|
$display("Image testing failed! Failed to write PCI Device Control register! Time %t ", image_num, $time) ;
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$display("Image testing failed! Failed to write PCI Device Control register! Time %t ", $time) ;
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test_fail("write to PCI Device Control register didn't succeede");
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test_fail("write to PCI Device Control register didn't succeede");
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disable main ;
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disable main ;
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end
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end
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|
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config_write( err_cs_offset, 32'h0000_0000, 4'h1, ok) ;
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config_write( err_cs_offset, 32'h0000_0000, 4'h1, ok) ;
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if ( ok !== 1 )
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if ( ok !== 1 )
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begin
|
begin
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$display("Image testing failed! Failed to write WB Error Control and Status register! Time %t ", image_num, $time) ;
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$display("Image testing failed! Failed to write WB Error Control and Status register! Time %t ", $time) ;
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test_fail("write to WB Error Control and Status register didn't succeede");
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test_fail("write to WB Error Control and Status register didn't succeede");
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disable main ;
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disable main ;
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end
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end
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|
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// prepare image control register
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// prepare image control register
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| Line 19112... |
Line 19115... |
`else
|
`else
|
parameter bist_chain_length = 6 ;
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parameter bist_chain_length = 6 ;
|
`endif
|
`endif
|
`else
|
`else
|
`ifdef PCI_RAM_DONT_SHARE
|
`ifdef PCI_RAM_DONT_SHARE
|
bist_chain_length = 6 ;
|
parameter bist_chain_length = 6 ;
|
`else
|
`else
|
bist_chain_length = 4 ;
|
parameter bist_chain_length = 4 ;
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
task run_bist_test ;
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task run_bist_test ;
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reg [(bist_chain_length - 1):0] bist_result_vector ;
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reg [(bist_chain_length - 1):0] bist_result_vector ;
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| Line 19126... |
Line 19129... |
integer deadlock_count ;
|
integer deadlock_count ;
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begin
|
begin
|
|
|
test_name = "BIST FOR RAMS RUN" ;
|
test_name = "BIST FOR RAMS RUN" ;
|
|
|
SI = 0 ;
|
scanb_en = 0 ;
|
shift_DR = 0 ;
|
scanb_si = 0 ;
|
capture_DR = 0 ;
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scanb_rst = 0 ;
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extest = 0 ;
|
scanb_clk = 0 ;
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tck = 0 ;
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|
|
|
fork
|
fork
|
begin
|
begin
|
repeat(2)
|
repeat(2)
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@(posedge wb_clock) ;
|
@(posedge wb_clock) ;
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| Line 19143... |
Line 19145... |
repeat(2)
|
repeat(2)
|
@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
|
end
|
end
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join
|
join
|
|
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// test is run with forcing extest high
|
// test is run by reseting the test logic
|
extest <= 1'b1 ;
|
scanb_rst <= 1'b1 ;
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|
|
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// toggle scan clock for a few times
|
|
repeat (20)
|
|
#50 scanb_clk = !scanb_clk ;
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|
|
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// release bist reset
|
|
scanb_rst <= 1'b0 ;
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|
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bist_result_vector = 0 ;
|
bist_result_vector = 0 ;
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|
|
// result vector must be all 1s, because in RTL there cannot be a reason for BIST to fail
|
// result vector must be all 1s, because in RTL there cannot be a reason for BIST to fail
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fork
|
fork
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begin:scan
|
begin:scan
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while (bist_result_vector !== {bist_chain_length{1'b1}})
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while (bist_result_vector !== {bist_chain_length{1'b1}})
|
begin
|
begin
|
@(negedge tck) ;
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#1 ;
|
capture_DR <= #1 1'b1 ;
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@(posedge scanb_clk) ;
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@(negedge tck) ;
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scanb_en <= #1 1'b1 ;
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capture_DR <= #1 1'b0 ;
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shift_DR <= #1 1'b1 ;
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|
for (count = 0 ; count < bist_chain_length ; count = count + 1'b1)
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for (count = 0 ; count < bist_chain_length ; count = count + 1'b1)
|
begin
|
begin
|
@(negedge tck) ;
|
@(posedge scanb_clk) ;
|
bist_result_vector[count] = SO ;
|
bist_result_vector[count] = scanb_so ;
|
end
|
end
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|
|
shift_DR <= #1 1'b0 ;
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scanb_en <= #1 1'b0 ;
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end
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end
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#1 disable deadlock ;
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#1 disable deadlock ;
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@(negedge tck) ;
|
@(negedge scanb_clk) ;
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extest <= #1 1'b0 ;
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#1 disable scanb_clk_gen ;
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#1 ;
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disable tck_gen ;
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test_ok ;
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test_ok ;
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end
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end
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begin:deadlock
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begin:deadlock
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for (deadlock_count = 0; deadlock_count <= 100000; deadlock_count = deadlock_count + 1'b1)
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for (deadlock_count = 0; deadlock_count <= 100000; deadlock_count = deadlock_count + 1'b1)
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begin
|
begin
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@(posedge pci_clock) ;
|
@(posedge pci_clock) ;
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@(posedge wb_clock) ;
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@(posedge wb_clock) ;
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end
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end
|
|
|
test_fail("BIST Test didn't finish as expected") ;
|
test_fail("BIST Test didn't finish as expected") ;
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extest <= #1 1'b0 ;
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scanb_en <= #1 1'b0 ;
|
disable scan ;
|
disable scan ;
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@(negedge tck) ;
|
@(negedge scanb_clk) ;
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#1 ;
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#1 ;
|
disable tck_gen ;
|
disable scanb_clk_gen ;
|
end
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end
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begin:tck_gen
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begin:scanb_clk_gen
|
forever
|
forever
|
#50 tck = !tck ;
|
#50 scanb_clk = !scanb_clk ;
|
end
|
end
|
join
|
join
|
end
|
end
|
endtask // run_bist_test
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endtask // run_bist_test
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`endif
|
`endif
|
| Line 19245... |
Line 19250... |
|
|
// Set Base Address of IMAGE
|
// Set Base Address of IMAGE
|
config_write( ba_offset, Target_Base_Addr_R[1], 4'hF, ok_wb ) ;
|
config_write( ba_offset, Target_Base_Addr_R[1], 4'hF, ok_wb ) ;
|
if ( ok_wb !== 1 )
|
if ( ok_wb !== 1 )
|
begin
|
begin
|
$display("Image testing failed! Failed to write P_BA1 register! Time %t ", $time);
|
$display("Special Testcase didn't pass! Failed to write P_BA1 register! Time %t ", $time);
|
test_fail("PCI Base Address register 1 could not be written") ;
|
test_fail("PCI Base Address register 1 could not be written") ;
|
#1 ;
|
#1 ;
|
disable main ;
|
disable main ;
|
end
|
end
|
|
|
// Set Address Mask of IMAGE
|
// Set Address Mask of IMAGE
|
config_write( am_offset, Target_Addr_Mask_R[1], 4'hF, ok_wb ) ;
|
config_write( am_offset, Target_Addr_Mask_R[1], 4'hF, ok_wb ) ;
|
if ( ok_wb !== 1 )
|
if ( ok_wb !== 1 )
|
begin
|
begin
|
$display("Image testing failed! Failed to write P_AM1 register! Time %t ", $time);
|
$display("Special Testcase didn't pass! Failed to write P_AM1 register! Time %t ", $time);
|
test_fail("PCI Address Mask register 1 could not be written") ;
|
test_fail("PCI Address Mask register 1 could not be written") ;
|
#1 ;
|
#1 ;
|
disable main ;
|
disable main ;
|
end
|
end
|
|
|
// Disable all the features of the PCI Image 1
|
// Disable all the features of the PCI Image 1
|
config_write( ctrl_offset, 0, 4'hF, ok_wb ) ;
|
config_write( ctrl_offset, 0, 4'hF, ok_wb ) ;
|
if ( ok_wb !== 1 )
|
if ( ok_wb !== 1 )
|
begin
|
begin
|
$display("Image testing failed! Failed to write P_CTRL1 register! Time %t ", $time);
|
$display("Special Testcase didn't pass! Failed to write P_CTRL1 register! Time %t ", $time);
|
test_fail("PCI Image Control register 1 could not be written") ;
|
test_fail("PCI Image Control register 1 could not be written") ;
|
#1 ;
|
#1 ;
|
disable main ;
|
disable main ;
|
end
|
end
|
|
|
| Line 19642... |
Line 19647... |
if ( ok_pci !== 1'b1)
|
if ( ok_pci !== 1'b1)
|
begin
|
begin
|
test_fail("PCI Behavioral Master or Monitor signaled an error during read from PCI Bridge Target") ;
|
test_fail("PCI Behavioral Master or Monitor signaled an error during read from PCI Bridge Target") ;
|
end
|
end
|
|
|
|
// Disable used image
|
|
config_write( ba_offset, 32'h0000_0000, 4'hF, ok_wb ) ;
|
|
if ( ok_wb !== 1 )
|
|
begin
|
|
$display("Special Testcase didn't pass! Failed to write P_BA1 register! Time %t ", $time);
|
|
test_fail("PCI Base Address register 1 could not be written") ;
|
|
#1 ;
|
|
disable main ;
|
|
end
|
|
|
master1_check_received_data = master_check_data_previous ;
|
master1_check_received_data = master_check_data_previous ;
|
end
|
end
|
endtask // target_special_corner_case_test
|
endtask // target_special_corner_case_test
|
`endif
|
`endif
|
|
|
|
`ifdef PCI_CLOCK_FOLLOWS_WB_CLOCK
|
|
task master_special_corner_case_test ;
|
|
reg [11:0] ctrl_offset ;
|
|
reg [11:0] ba_offset ;
|
|
reg [11:0] am_offset ;
|
|
reg `WRITE_STIM_TYPE write_data ;
|
|
reg `READ_STIM_TYPE read_data ;
|
|
reg `READ_RETURN_TYPE read_status ;
|
|
|
|
reg `WRITE_RETURN_TYPE write_status ;
|
|
reg `WB_TRANSFER_FLAGS flags ;
|
|
reg ok_pci ;
|
|
reg ok_wb ;
|
|
|
|
reg [31:0] target_address ;
|
|
|
|
reg [11:0] pci_ctrl_offset ;
|
|
|
|
reg [31:0] image_base ;
|
|
begin:main
|
|
test_name = "WISHBONE SLAVE UNIT SPECIAL CORNER CASE" ;
|
|
pci_ctrl_offset = 12'h4 ;
|
|
ctrl_offset = {4'h1, `W_IMG_CTRL1_ADDR, 2'b00} ;
|
|
ba_offset = {4'h1, `W_BA1_ADDR, 2'b00} ;
|
|
am_offset = {4'h1, `W_AM1_ADDR, 2'b00} ;
|
|
|
|
target_address = `BEH_TAR1_MEM_START ;
|
|
image_base = 0 ;
|
|
image_base[`PCI_BASE_ADDR0_MATCH_RANGE] = target_address[`PCI_BASE_ADDR0_MATCH_RANGE] ;
|
|
|
|
target_address[31:(32 - `WB_NUM_OF_DEC_ADDR_LINES)] = image_base[31:(32 - `WB_NUM_OF_DEC_ADDR_LINES)] ;
|
|
target_address[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] = image_base[(31 - `WB_NUM_OF_DEC_ADDR_LINES):0] ;
|
|
|
|
flags = 0 ;
|
|
flags`INIT_WAITS = 0 ;
|
|
flags`SUBSEQ_WAITS = 0 ;
|
|
flags`WB_TRANSFER_AUTO_RTY = 0 ;
|
|
|
|
test_target_response[`TARGET_ENCODED_DEVSEL_SPEED] = `Test_Devsel_Fast ;
|
|
test_target_response[`TARGET_ENCODED_INIT_WAITSTATES] = 0 ;
|
|
test_target_response[`TARGET_ENCODED_SUBS_WAITSTATES] = 0 ;
|
|
|
|
// enable master & target operation
|
|
config_write( pci_ctrl_offset, 32'h0000_0007, 4'h1, ok_wb) ;
|
|
if ( ok_wb !== 1 )
|
|
begin
|
|
$display("WISHBONE Slave Unit special corner case test didn't pass! Failed to write PCI Device Control register! Time %t ", $time) ;
|
|
test_fail("write to PCI Device Control register didn't succeede");
|
|
disable main ;
|
|
end
|
|
|
|
// prepare image control register
|
|
config_write( ctrl_offset, 32'h0000_0000, 4'hF, ok_wb) ;
|
|
if ( ok_wb !== 1 )
|
|
begin
|
|
$display("WISHBONE Slave Unit special corner case test didn't pass! Failed to write W_IMG_CTRL1 register! Time %t ", $time) ;
|
|
test_fail("write to WB Image Control register didn't succeede");
|
|
disable main ;
|
|
end
|
|
|
|
// prepare base address register
|
|
config_write( ba_offset, image_base, 4'hF, ok_wb ) ;
|
|
if ( ok_wb !== 1 )
|
|
begin
|
|
$display("WISHBONE Slave Unit special corner case test didn't pass! Failed to write W_BA1 register! Time %t ", $time) ;
|
|
test_fail("write to WB Base Address register didn't succeede");
|
|
disable main ;
|
|
end
|
|
|
|
// write address mask register
|
|
config_write( am_offset, 32'hFFFF_FFFF, 4'hF, ok_wb ) ;
|
|
if ( ok_wb !== 1 )
|
|
begin
|
|
$display("WISHBONE Slave Unit special corner case test didn't pass! Failed to write W_AM1 register! Time %t ", $time) ;
|
|
test_fail("write to WB Address Mask register didn't succeede");
|
|
disable main ;
|
|
end
|
|
|
|
fork
|
|
begin
|
|
|
|
// do one dummy read, to receive bus gnt
|
|
read_data`READ_ADDRESS = target_address ;
|
|
read_data`READ_SEL = 4'hF ;
|
|
read_data`READ_TAG_STIM = 0 ;
|
|
|
|
// handle retries
|
|
flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
|
|
|
wishbone_master.wb_single_read( read_data, flags, read_status ) ;
|
|
if (read_status`CYC_ACTUAL_TRANSFER !== 1)
|
|
begin
|
|
$display("WISHBONE Slave Unit special corner case test didn't pass! Bridge failed to process single memory read! Time %t ", $time) ;
|
|
test_fail("PCI bridge didn't process the delayed read as expected");
|
|
disable main ;
|
|
end
|
|
|
|
write_data`WRITE_ADDRESS = target_address + 64;
|
|
write_data`WRITE_DATA = 32'hABCD_EF12 ;
|
|
write_data`WRITE_SEL = 4'hF ;
|
|
|
|
wishbone_master.blk_write_data[0] = write_data ;
|
|
|
|
write_data`WRITE_ADDRESS = target_address + 128 ;
|
|
write_data`WRITE_DATA = ~write_data`WRITE_DATA ;
|
|
write_data`WRITE_SEL = 4'hF ;
|
|
|
|
wishbone_master.blk_write_data[1] = write_data ;
|
|
|
|
// no retries should happen
|
|
flags`WB_TRANSFER_AUTO_RTY = 0 ;
|
|
|
|
flags`WB_TRANSFER_SIZE = 2 ;
|
|
|
|
wishbone_master.wb_block_write( flags, write_status ) ;
|
|
if ( write_status`CYC_ACTUAL_TRANSFER !== 2 )
|
|
begin
|
|
$display("WISHBONE Slave Unit special corner case test didn't pass! Bridge failed to process block memory write! Time %t ", $time) ;
|
|
test_fail("WB Slave state machine failed to post block memory write");
|
|
disable main ;
|
|
end
|
|
|
|
// read data back
|
|
read_data`READ_ADDRESS = target_address + 64 ;
|
|
read_data`READ_SEL = 4'hF ;
|
|
read_data`READ_TAG_STIM = 0 ;
|
|
|
|
// handle retries
|
|
flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
|
|
|
wishbone_master.wb_single_read( read_data, flags, read_status ) ;
|
|
if (read_status`CYC_ACTUAL_TRANSFER !== 1)
|
|
begin
|
|
$display("WISHBONE Slave Unit special corner case test didn't pass! Bridge failed to process single memory read! Time %t ", $time) ;
|
|
test_fail("PCI bridge didn't process the delayed read as expected");
|
|
disable main ;
|
|
end
|
|
|
|
if (read_status`READ_DATA !== 32'hABCD_EF12)
|
|
begin
|
|
display_warning(target_address + 64, 32'hABCD_EF12, read_status`READ_DATA) ;
|
|
test_fail("PCI bridge returned unexpected Read Data");
|
|
ok_wb = 0 ;
|
|
end
|
|
|
|
// read second data back
|
|
read_data`READ_ADDRESS = target_address + 128 ;
|
|
read_data`READ_SEL = 4'hF ;
|
|
read_data`READ_TAG_STIM = 0 ;
|
|
|
|
// handle retries
|
|
flags`WB_TRANSFER_AUTO_RTY = 1 ;
|
|
|
|
wishbone_master.wb_single_read( read_data, flags, read_status ) ;
|
|
if (read_status`CYC_ACTUAL_TRANSFER !== 1)
|
|
begin
|
|
$display("WISHBONE Slave Unit special corner case test didn't pass! Bridge failed to process single memory read! Time %t ", $time) ;
|
|
test_fail("PCI bridge didn't process the delayed read as expected");
|
|
disable main ;
|
|
end
|
|
|
|
if (read_status`READ_DATA !== write_data`WRITE_DATA)
|
|
begin
|
|
display_warning(target_address + 128, write_data`WRITE_DATA, read_status`READ_DATA) ;
|
|
test_fail("PCI bridge returned unexpected Read Data");
|
|
ok_wb = 0 ;
|
|
end
|
|
end
|
|
begin
|
|
|
|
pci_transaction_progress_monitor( target_address, `BC_MEM_READ, 1, 0, 1, 0, 0, ok_pci ) ;
|
|
if ( ok_pci !== 1 )
|
|
begin
|
|
test_fail("because single memory read from WB to PCI didn't engage expected transaction on PCI bus") ;
|
|
end
|
|
|
|
if(ok_pci)
|
|
begin
|
|
pci_transaction_progress_monitor( target_address + 64, `BC_MEM_WRITE, 1, 0, 1, 0, 0, ok_pci ) ;
|
|
if ( ok_pci !== 1 )
|
|
begin
|
|
test_fail("because single memory write from WB to PCI didn't engage expected transaction on PCI bus") ;
|
|
end
|
|
end
|
|
|
|
if (ok_pci)
|
|
begin
|
|
pci_transaction_progress_monitor( target_address + 128, `BC_MEM_WRITE, 1, 0, 1, 0, 0, ok_pci ) ;
|
|
if ( ok_pci !== 1 )
|
|
begin
|
|
test_fail("because single memory write from WB to PCI didn't engage expected transaction on PCI bus") ;
|
|
end
|
|
end
|
|
|
|
if (ok_pci)
|
|
begin
|
|
pci_transaction_progress_monitor( target_address + 64, `BC_MEM_READ, 1, 0, 1, 0, 0, ok_pci ) ;
|
|
if ( ok_pci !== 1 )
|
|
begin
|
|
test_fail("because single memory read from WB to PCI didn't engage expected transaction on PCI bus") ;
|
|
end
|
|
end
|
|
|
|
if (ok_pci)
|
|
begin
|
|
pci_transaction_progress_monitor( target_address + 128, `BC_MEM_READ, 1, 0, 1, 0, 0, ok_pci ) ;
|
|
if ( ok_pci !== 1 )
|
|
begin
|
|
test_fail("because single memory read from WB to PCI didn't engage expected transaction on PCI bus") ;
|
|
end
|
|
end
|
|
end
|
|
join
|
|
|
|
if (ok_wb && ok_pci)
|
|
test_ok ;
|
|
|
|
// disable the image
|
|
config_write( ba_offset, 32'h0000_0000, 4'hF, ok_wb ) ;
|
|
if ( ok_wb !== 1 )
|
|
begin
|
|
$display("WISHBONE Slave Unit special corner case test didn't pass! Failed to write W_BA1 register! Time %t ", $time) ;
|
|
test_fail("write to WB Base Address register didn't succeede");
|
|
disable main ;
|
|
end
|
|
end
|
|
endtask // master_special_corner_case_test
|
|
`endif
|
|
|
task test_fail ;
|
task test_fail ;
|
input [7999:0] failure_reason ;
|
input [7999:0] failure_reason ;
|
reg [8007:0] display_failure ;
|
reg [8007:0] display_failure ;
|
reg [799:0] display_test ;
|
reg [799:0] display_test ;
|
begin
|
begin
|
