| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2003/08/03 18:04:44 mihad
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// Added limited WISHBONE B3 support for WISHBONE Slave Unit.
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// Doesn't support full speed bursts yet.
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//
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// Revision 1.2 2002/08/13 11:03:51 mihad
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// Revision 1.2 2002/08/13 11:03:51 mihad
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// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
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// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
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//
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//
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// Revision 1.1 2002/02/01 13:39:43 mihad
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// Revision 1.1 2002/02/01 13:39:43 mihad
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// Initial testbench import. Still under development
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// Initial testbench import. Still under development
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| Line 71... |
Line 75... |
STB_O,
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STB_O,
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WE_O,
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WE_O,
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TAG_I,
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TAG_I,
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TAG_O,
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TAG_O,
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CAB_O,
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CAB_O,
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check_CTI,
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log_file_desc
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log_file_desc
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) ;
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) ;
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input CLK_I ;
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input CLK_I ;
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input RST_I ;
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input RST_I ;
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| Line 89... |
Line 94... |
input STB_O ;
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input STB_O ;
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input WE_O ;
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input WE_O ;
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input [(`WB_TAG_WIDTH-1):0] TAG_I ;
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input [(`WB_TAG_WIDTH-1):0] TAG_I ;
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input [(`WB_TAG_WIDTH-1):0] TAG_O ;
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input [(`WB_TAG_WIDTH-1):0] TAG_O ;
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input CAB_O ;
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input CAB_O ;
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input check_CTI ;
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input [31:0] log_file_desc ;
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input [31:0] log_file_desc ;
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always@(posedge CLK_I)
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always@(posedge CLK_I)
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begin
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begin
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if (RST_I !== 1'b0)
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if (RST_I !== 1'b0)
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| Line 337... |
Line 343... |
$fdisplay(log_file_desc, "CAB_O value changed during cycle") ;
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$fdisplay(log_file_desc, "CAB_O value changed during cycle") ;
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end
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end
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end
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end
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end // CAB_O monitor
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end // CAB_O monitor
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// CTI_O[2:0] (TAG_O[4:2]) monitor for bursts
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reg [2:0] first_cti_val ;
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always@(posedge CLK_I or posedge RST_I)
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begin
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if (RST_I)
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first_cti_val <= 3'b000 ;
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// logging for burst cycle
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else if ( check_CTI && ((CYC_O === 0) && (first_cti_val == 3'b011) && ~(previous_rty || previous_err)))
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begin
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message_out("Master violated WISHBONE protocol by NOT changing the CTI_O signals to '111' when end of burst!") ;
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$display("CTI_O didn't change to '111' when end of burst") ;
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$fdisplay(log_file_desc, "CTI_O didn't change to '111' when end of burst") ;
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first_cti_val <= 3'b000 ;
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end
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else if (CYC_O === 0)
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first_cti_val <= 3'b000 ;
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else
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begin
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if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b000) && (ACK_I || ERR_I || RTY_I))
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first_cti_val <= 3'b001 ;
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else if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b111) && (ACK_I || ERR_I || RTY_I))
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first_cti_val <= 3'b010 ;
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else if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b010) && (ACK_I || ERR_I || RTY_I))
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first_cti_val <= 3'b011 ;
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else if ((first_cti_val == 3'b011) && (TAG_O[4:2] === 3'b111) && (ACK_I || ERR_I || RTY_I))
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first_cti_val <= 3'b010 ;
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// logging for clasic cycles
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else if (check_CTI && ((first_cti_val == 3'b001) && (TAG_O[4:2] !== 3'b000)))
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begin
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message_out("Master violated WISHBONE protocol by changing the CTI_O signals during CYC_O when clasic cycle!") ;
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$display("CTI_O change during CYC_O when clasic cycle") ;
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$fdisplay(log_file_desc, "CTI_O change during CYC_O when clasic cycle") ;
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end
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// logging for end of burs cycle
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else if (check_CTI && (first_cti_val == 3'b010))
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begin
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message_out("Master violated WISHBONE protocol by changing the CTI_O signals to '111' before end of burst!") ;
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$display("CTI_O change to '111' before end of burst") ;
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$fdisplay(log_file_desc, "CTI_O change to '111' before end of burst") ;
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end
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end
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end
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// WE_O monitor for consecutive address bursts
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// WE_O monitor for consecutive address bursts
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reg [1:0] first_we_val ;
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reg [1:0] first_we_val ;
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always@(posedge CLK_I or posedge RST_I)
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always@(posedge CLK_I or posedge RST_I)
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begin
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begin
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if (~CYC_O || ~CAB_O || RST_I)
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if (~CYC_O || ~CAB_O || RST_I)
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