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[/] [pci/] [tags/] [rel_9/] [bench/] [verilog/] [wb_master32.v] - Diff between revs 15 and 92
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Rev 92 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/02/01 13:39:43 mihad
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// Initial testbench import. Still under development
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//
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//
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//
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`include "pci_testbench_defines.v"
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`include "pci_testbench_defines.v"
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`include "timescale.v"
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`include "timescale.v"
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module WB_MASTER32
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module WB_MASTER32
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reg we ;
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reg we ;
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task start_cycle ;
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task start_cycle ;
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input is_cab ;
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input is_cab ;
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input write ;
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input write ;
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input fastb2b ;
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output ok ; // ok indicates to the caller that cycle was started succesfully - if not, caller must take appropriate action
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output ok ; // ok indicates to the caller that cycle was started succesfully - if not, caller must take appropriate action
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begin:main
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begin:main
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ok = 1 ;
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ok = 1 ;
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end
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end
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if ( (cycle_in_progress === 1) || (CYC_O === 1))
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if ( (cycle_in_progress === 1) || (CYC_O === 1))
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begin
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begin
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// cycle was previously started - allow cycle to continue if CAB and WE values match
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// cycle was previously started - allow cycle to continue if CAB and WE values match
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if (fastb2b !== 1'b1)
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$display("*W, cycle already in progress when start_cycle routine was called! Time %t ", $time) ;
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$display("*W, cycle already in progress when start_cycle routine was called! Time %t ", $time) ;
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if ((CAB_O !== is_cab) || (WE_O !== write) )
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if ((CAB_O !== is_cab) || (WE_O !== write) )
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begin
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begin
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ok = 0 ;
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ok = 0 ;
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if ( is_cab === 1 )
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if ( is_cab === 1 )
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$display("*E, cab cycle start attempted when non-cab cycle was in progress! Time %t", $time) ;
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$display("*E, cab cycle start attempted when non-cab cycle was in progress! Time %t", $time) ;
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