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[/] [pci/] [tags/] [rel_9/] [bench/] [verilog/] [wb_slave_behavioral.v] - Diff between revs 104 and 119
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Rev 119 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2003/07/29 08:19:47 mihad
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// Found and simulated the problem in the synchronization logic.
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// Repaired the synchronization logic in the FIFOs.
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//
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// Revision 1.4 2003/06/12 02:30:39 mihad
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// Revision 1.4 2003/06/12 02:30:39 mihad
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// Update!
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// Update!
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//
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//
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// Revision 1.3 2002/10/11 10:08:58 mihad
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// Revision 1.3 2002/10/11 10:08:58 mihad
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// Added additional testcase and changed rst name in BIST to trst
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// Added additional testcase and changed rst name in BIST to trst
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ERR_O,
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ERR_O,
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RTY_O,
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RTY_O,
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SEL_I,
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SEL_I,
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STB_I,
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STB_I,
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WE_I,
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WE_I,
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CAB_I
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CTI_I,
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BTE_I
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);
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);
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/*------------------------------------------------------------------------------------------------------
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/*------------------------------------------------------------------------------------------------------
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WISHBONE signals
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WISHBONE signals
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------------------------------------------------------------------------------------------------------*/
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------------------------------------------------------------------------------------------------------*/
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output ERR_O;
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output ERR_O;
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output RTY_O;
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output RTY_O;
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input `WB_SEL_TYPE SEL_I;
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input `WB_SEL_TYPE SEL_I;
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input STB_I;
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input STB_I;
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input WE_I;
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input WE_I;
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input CAB_I;
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input [2:0] CTI_I;
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input [1:0] BTE_I;
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reg `WB_DATA_TYPE DAT_O;
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reg `WB_DATA_TYPE DAT_O;
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/*------------------------------------------------------------------------------------------------------
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/*------------------------------------------------------------------------------------------------------
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Asynchronous dual-port RAM signals for storing and fetching the data
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Asynchronous dual-port RAM signals for storing and fetching the data
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