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[/] [pci/] [tags/] [rel_9/] [bench/] [verilog/] [wb_slave_behavioral.v] - Diff between revs 63 and 92
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| Rev 63 |
Rev 92 |
| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/10/11 10:08:58 mihad
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// Added additional testcase and changed rst name in BIST to trst
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//
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// Revision 1.2 2002/03/06 09:10:56 mihad
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// Revision 1.2 2002/03/06 09:10:56 mihad
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// Added missing include statements
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// Added missing include statements
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//
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//
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// Revision 1.1 2002/02/01 13:39:43 mihad
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// Revision 1.1 2002/02/01 13:39:43 mihad
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// Initial testbench import. Still under development
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// Initial testbench import. Still under development
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Line 232... |
retry_expired = 1'b0;
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retry_expired = 1'b0;
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end
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end
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else
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else
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begin
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begin
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retry_num = retry_cnt;
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retry_num = retry_cnt;
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if (max_retry != 8'h0)
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retry_expired = 1'b1;
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retry_expired = 1'b1;
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end
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end
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end
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end
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reg [3:0] wait_cnt;
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reg [3:0] wait_cnt;
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Line 388... |
DAT_O <=#1 mem_rd_data_in;
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DAT_O <=#1 mem_rd_data_in;
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else
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else
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DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx;
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DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx;
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end
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end
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*/
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*/
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wire `WB_DATA_TYPE current_memory_location = wb_memory[ADR_I[21:2]] ;
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always@
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always@
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(
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(
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RST_I or
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RST_I or
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ACK_O or
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ACK_O or
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WE_I or
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WE_I or
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ADR_I
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current_memory_location
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)
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)
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begin
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begin
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if ((ACK_O === 1'b1) && (RST_I === 1'b0) && (WE_I === 1'b0))
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if ((ACK_O === 1'b1) && (RST_I === 1'b0) && (WE_I === 1'b0))
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DAT_O <= #1 wb_memory[ADR_I[21:2]] ;
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DAT_O <= #1 current_memory_location ;
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else
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else
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DAT_O <= #1 {`WB_DATA_WIDTH{1'bx}} ;
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DAT_O <= #1 {`WB_DATA_WIDTH{1'bx}} ;
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end
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end
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always@(RST_I or task_rd_adr_i)
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always@(RST_I or task_rd_adr_i)
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