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[/] [pci/] [tags/] [rel_9/] [rtl/] [verilog/] [pci_io_mux_ad_en_crit.v] - Diff between revs 18 and 77
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/02/01 14:43:31 mihad
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// *** empty log message ***
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//
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//
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//
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// module provides equation for ad output enables, which uses critical pci bus inputs
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// module provides equation for ad output enables, which uses critical pci bus inputs
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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// module is provided for ad bus output enable Flip-Flops values
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// module is provided for ad bus output enable Flip-Flops values
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module PCI_IO_MUX_AD_EN_CRIT
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module pci_io_mux_ad_en_crit
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(
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(
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ad_en_in,
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ad_en_in,
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pci_frame_in,
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pci_frame_in,
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pci_trdy_in,
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pci_trdy_in,
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pci_stop_in,
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pci_stop_in,
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pci_stop_in ;
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pci_stop_in ;
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output ad_en_out ;
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output ad_en_out ;
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assign ad_en_out = ad_en_in && ( ~pci_frame_in || (pci_trdy_in && pci_stop_in) ) ;
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assign ad_en_out = ad_en_in && ( ~pci_frame_in || (pci_trdy_in && pci_stop_in) ) ;
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endmodule
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endmodule
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