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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.13 2003/08/21 20:55:14 tadejm
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// Corrected bug when writing to FIFO (now it is registered).
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//
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// Revision 1.12 2003/08/08 16:36:33 tadejm
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// Revision 1.12 2003/08/08 16:36:33 tadejm
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// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
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// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
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//
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//
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// Revision 1.11 2003/01/27 16:49:31 mihad
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// Revision 1.11 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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//
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// Revision 1.10 2002/10/18 03:36:37 tadejm
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// Revision 1.10 2002/10/18 03:36:37 tadejm
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// Changed wrong signal name scanb_sen into scanb_en.
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// Changed wrong signal name mbist_sen into mbist_ctrl_i.
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//
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//
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// Revision 1.9 2002/10/17 22:51:08 tadejm
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// Revision 1.9 2002/10/17 22:51:08 tadejm
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// Changed BIST signals for RAMs.
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// Changed BIST signals for RAMs.
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//
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//
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// Revision 1.8 2002/10/11 10:09:01 mihad
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// Revision 1.8 2002/10/11 10:09:01 mihad
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| Line 179... |
Line 182... |
pciu_pciw_fifo_empty_out
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pciu_pciw_fifo_empty_out
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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// debug chain signals
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// debug chain signals
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scanb_rst, // bist scan reset
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mbist_si_i, // bist scan serial in
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scanb_clk, // bist scan clock
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mbist_so_o, // bist scan serial out
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scanb_si, // bist scan serial in
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mbist_ctrl_i // bist chain shift control
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scanb_so, // bist scan serial out
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scanb_en // bist scan shift enable
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`endif
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`endif
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);
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);
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input reset_in,
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input reset_in,
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wb_clock_in,
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wb_clock_in,
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| Line 288... |
Line 289... |
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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/*-----------------------------------------------------
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/*-----------------------------------------------------
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BIST debug chain port signals
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BIST debug chain port signals
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-----------------------------------------------------*/
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-----------------------------------------------------*/
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input scanb_rst; // bist scan reset
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input mbist_si_i; // bist scan serial in
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input scanb_clk; // bist scan clock
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output mbist_so_o; // bist scan serial out
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input scanb_si; // bist scan serial in
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input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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output scanb_so; // bist scan serial out
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input scanb_en; // bist scan shift enable
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`endif
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`endif
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// pci target state machine and interface outputs
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// pci target state machine and interface outputs
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wire pcit_sm_trdy_out ;
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wire pcit_sm_trdy_out ;
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Line 580... |
.pcir_empty_out (fifos_pcir_empty_out), //for PCI Target !!!
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.pcir_empty_out (fifos_pcir_empty_out), //for PCI Target !!!
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.pcir_transaction_ready_out ()
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.pcir_transaction_ready_out ()
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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.scanb_rst (scanb_rst),
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.mbist_si_i (mbist_si_i),
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.scanb_clk (scanb_clk),
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.mbist_so_o (mbist_so_o),
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.scanb_si (scanb_si),
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.mbist_ctrl_i (mbist_ctrl_i)
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.scanb_so (scanb_so),
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.scanb_en (scanb_en)
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`endif
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`endif
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) ;
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) ;
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// delayed transaction logic inputs
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// delayed transaction logic inputs
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wire del_sync_req_in = pcit_if_req_out ;
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wire del_sync_req_in = pcit_if_req_out ;
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