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Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2002/10/18 03:36:37 tadejm
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// Changed wrong signal name scanb_sen into scanb_en.
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//
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// Revision 1.9 2002/10/17 22:51:08 tadejm
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// Revision 1.9 2002/10/17 22:51:08 tadejm
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// Changed BIST signals for RAMs.
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// Changed BIST signals for RAMs.
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//
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//
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// Revision 1.8 2002/10/11 10:09:01 mihad
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// Revision 1.8 2002/10/11 10:09:01 mihad
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// Added additional testcase and changed rst name in BIST to trst
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// Added additional testcase and changed rst name in BIST to trst
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| Line 78... |
Line 81... |
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module PCI_TARGET_UNIT
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module pci_target_unit
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(
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(
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reset_in,
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reset_in,
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wb_clock_in,
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wb_clock_in,
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pci_clock_in,
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pci_clock_in,
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ADR_O,
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ADR_O,
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| Line 465... |
Line 468... |
wire wbm_sm_ack_in = ACK_I ;
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wire wbm_sm_ack_in = ACK_I ;
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wire wbm_sm_rty_in = RTY_I ;
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wire wbm_sm_rty_in = RTY_I ;
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wire wbm_sm_err_in = ERR_I ;
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wire wbm_sm_err_in = ERR_I ;
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// WISHBONE master interface instantiation
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// WISHBONE master interface instantiation
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WB_MASTER wishbone_master
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pci_wb_master wishbone_master
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(
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(
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.wb_clock_in (wb_clock_in),
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.wb_clock_in (wb_clock_in),
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.reset_in (reset_in),
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.reset_in (reset_in),
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.pci_tar_read_request (wbm_sm_pci_tar_read_request), //in
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.pci_tar_read_request (wbm_sm_pci_tar_read_request), //in
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.pci_tar_address (wbm_sm_pci_tar_address), //in
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.pci_tar_address (wbm_sm_pci_tar_address), //in
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| Line 525... |
Line 528... |
wire [3:0] fifos_pcir_control_in = wbm_sm_pcir_fifo_control_out ;
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wire [3:0] fifos_pcir_control_in = wbm_sm_pcir_fifo_control_out ;
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wire fifos_pcir_renable_in = pcit_if_pcir_fifo_renable_out ;
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wire fifos_pcir_renable_in = pcit_if_pcir_fifo_renable_out ;
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wire fifos_pcir_flush_in = pcit_if_pcir_fifo_flush_out ;
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wire fifos_pcir_flush_in = pcit_if_pcir_fifo_flush_out ;
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// PCIW_FIFO and PCIR_FIFO instantiation
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// PCIW_FIFO and PCIR_FIFO instantiation
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PCIW_PCIR_FIFOS fifos
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pci_pciw_pcir_fifos fifos
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(
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(
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.wb_clock_in (wb_clock_in),
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.wb_clock_in (wb_clock_in),
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.pci_clock_in (pci_clock_in),
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.pci_clock_in (pci_clock_in),
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.reset_in (reset_in),
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.reset_in (reset_in),
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.pciw_wenable_in (fifos_pciw_wenable_in), //for PCI Target !!!
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.pciw_wenable_in (fifos_pciw_wenable_in), //for PCI Target !!!
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| Line 583... |
Line 586... |
wire del_sync_status_in = 1'b0 ;
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wire del_sync_status_in = 1'b0 ;
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wire del_sync_burst_in = pcit_if_burst_ok_out ;
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wire del_sync_burst_in = pcit_if_burst_ok_out ;
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wire del_sync_retry_expired_in = wbm_sm_read_rty_cnt_exp_out ;
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wire del_sync_retry_expired_in = wbm_sm_read_rty_cnt_exp_out ;
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// delayed transaction logic instantiation
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// delayed transaction logic instantiation
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DELAYED_SYNC del_sync
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pci_delayed_sync del_sync
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(
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(
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.reset_in (reset_in),
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.reset_in (reset_in),
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.req_clk_in (pci_clock_in),
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.req_clk_in (pci_clock_in),
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.comp_clk_in (wb_clock_in),
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.comp_clk_in (wb_clock_in),
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.req_in (del_sync_req_in),
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.req_in (del_sync_req_in),
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| Line 689... |
Line 692... |
wire pcit_if_addr_tran_en2_in = pciu_at_en_in[2] ;
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wire pcit_if_addr_tran_en2_in = pciu_at_en_in[2] ;
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wire pcit_if_addr_tran_en3_in = pciu_at_en_in[3] ;
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wire pcit_if_addr_tran_en3_in = pciu_at_en_in[3] ;
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wire pcit_if_addr_tran_en4_in = pciu_at_en_in[4] ;
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wire pcit_if_addr_tran_en4_in = pciu_at_en_in[4] ;
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wire pcit_if_addr_tran_en5_in = pciu_at_en_in[5] ;
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wire pcit_if_addr_tran_en5_in = pciu_at_en_in[5] ;
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PCI_TARGET32_INTERFACE pci_target_if
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pci_target32_interface pci_target_if
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(
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(
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.clk_in (pci_clock_in),
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.clk_in (pci_clock_in),
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.reset_in (reset_in),
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.reset_in (reset_in),
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.address_in (pcit_if_address_in),
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.address_in (pcit_if_address_in),
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.addr_claim_out (pcit_if_addr_claim_out),
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.addr_claim_out (pcit_if_addr_claim_out),
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| Line 834... |
Line 837... |
wire pcit_sm_wbu_frame_en_in = pciu_wbu_frame_en_in ;
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wire pcit_sm_wbu_frame_en_in = pciu_wbu_frame_en_in ;
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wire pcit_sm_trdy_reg_in = pciu_pciif_trdy_reg_in ;
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wire pcit_sm_trdy_reg_in = pciu_pciif_trdy_reg_in ;
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wire pcit_sm_stop_reg_in = pciu_pciif_stop_reg_in ;
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wire pcit_sm_stop_reg_in = pciu_pciif_stop_reg_in ;
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PCI_TARGET32_SM pci_target_sm
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pci_target32_sm pci_target_sm
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(
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(
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.clk_in (pci_clock_in),
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.clk_in (pci_clock_in),
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.reset_in (reset_in),
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.reset_in (reset_in),
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.pci_frame_in (pcit_sm_frame_in),
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.pci_frame_in (pcit_sm_frame_in),
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.pci_irdy_in (pcit_sm_irdy_in),
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.pci_irdy_in (pcit_sm_irdy_in),
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