URL
https://opencores.org/ocsvn/pci/pci/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 77 |
Rev 106 |
| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.9 2003/01/27 16:49:31 mihad
|
|
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
|
|
//
|
// Revision 1.8 2002/10/18 03:36:37 tadejm
|
// Revision 1.8 2002/10/18 03:36:37 tadejm
|
// Changed wrong signal name scanb_sen into scanb_en.
|
// Changed wrong signal name scanb_sen into scanb_en.
|
//
|
//
|
// Revision 1.7 2002/10/17 22:49:22 tadejm
|
// Revision 1.7 2002/10/17 22:49:22 tadejm
|
// Changed BIST signals for RAMs.
|
// Changed BIST signals for RAMs.
|
| Line 108... |
Line 111... |
SEL_I,
|
SEL_I,
|
CYC_I,
|
CYC_I,
|
STB_I,
|
STB_I,
|
WE_I,
|
WE_I,
|
CAB_I,
|
CAB_I,
|
|
CTI_I,
|
|
BTE_I,
|
ACK_O,
|
ACK_O,
|
RTY_O,
|
RTY_O,
|
ERR_O,
|
ERR_O,
|
|
|
// WISHBONE master interface
|
// WISHBONE master interface
|
| Line 169... |
Line 174... |
input [3:0] SEL_I ;
|
input [3:0] SEL_I ;
|
input CYC_I ;
|
input CYC_I ;
|
input STB_I ;
|
input STB_I ;
|
input WE_I ;
|
input WE_I ;
|
input CAB_I ;
|
input CAB_I ;
|
|
input [ 2:0] CTI_I ;
|
|
input [ 1:0] BTE_I ;
|
output ACK_O ;
|
output ACK_O ;
|
output RTY_O ;
|
output RTY_O ;
|
output ERR_O ;
|
output ERR_O ;
|
|
|
// WISHBONE master interface
|
// WISHBONE master interface
|
| Line 268... |
Line 275... |
.wbs_dat_o(SDAT_O),
|
.wbs_dat_o(SDAT_O),
|
.wbs_sel_i(SEL_I),
|
.wbs_sel_i(SEL_I),
|
.wbs_cyc_i(CYC_I),
|
.wbs_cyc_i(CYC_I),
|
.wbs_stb_i(STB_I),
|
.wbs_stb_i(STB_I),
|
.wbs_we_i (WE_I),
|
.wbs_we_i (WE_I),
|
|
|
|
`ifdef PCI_WB_REV_B3
|
|
|
|
.wbs_cti_i(CTI_I),
|
|
.wbs_bte_i(BTE_I),
|
|
|
|
`else
|
|
|
.wbs_cab_i(CAB_I),
|
.wbs_cab_i(CAB_I),
|
|
|
|
`endif
|
|
|
.wbs_ack_o(ACK_O),
|
.wbs_ack_o(ACK_O),
|
.wbs_rty_o(RTY_O),
|
.wbs_rty_o(RTY_O),
|
.wbs_err_o(ERR_O),
|
.wbs_err_o(ERR_O),
|
|
|
// WISHBONE master interface
|
// WISHBONE master interface
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.