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[/] [pci/] [tags/] [rel_9/] [rtl/] [verilog/] [top.v] - Diff between revs 106 and 115
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Rev 106 |
Rev 115 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2003/08/03 18:05:06 mihad
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// Added limited WISHBONE B3 support for WISHBONE Slave Unit.
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// Doesn't support full speed bursts yet.
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//
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// Revision 1.9 2003/01/27 16:49:31 mihad
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// Revision 1.9 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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//
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// Revision 1.8 2002/10/18 03:36:37 tadejm
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// Revision 1.8 2002/10/18 03:36:37 tadejm
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// Changed wrong signal name scanb_sen into scanb_en.
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// Changed wrong signal name scanb_sen into scanb_en.
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Line 129... |
MDAT_O,
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MDAT_O,
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SEL_O,
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SEL_O,
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CYC_O,
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CYC_O,
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STB_O,
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STB_O,
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WE_O,
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WE_O,
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CAB_O,
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CTI_O,
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BTE_O,
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ACK_I,
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ACK_I,
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RTY_I,
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RTY_I,
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ERR_I
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ERR_I
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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output [31:0] MDAT_O ;
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output [31:0] MDAT_O ;
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output [3:0] SEL_O ;
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output [3:0] SEL_O ;
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output CYC_O ;
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output CYC_O ;
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output STB_O ;
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output STB_O ;
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output WE_O ;
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output WE_O ;
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output CAB_O ;
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output [2:0] CTI_O ;
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output [1:0] BTE_O ;
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input ACK_I ;
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input ACK_I ;
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input RTY_I ;
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input RTY_I ;
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input ERR_I ;
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input ERR_I ;
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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Line 299... |
Line 305... |
.wbm_dat_o(MDAT_O),
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.wbm_dat_o(MDAT_O),
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.wbm_sel_o(SEL_O),
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.wbm_sel_o(SEL_O),
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.wbm_cyc_o(CYC_O),
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.wbm_cyc_o(CYC_O),
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.wbm_stb_o(STB_O),
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.wbm_stb_o(STB_O),
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.wbm_we_o (WE_O),
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.wbm_we_o (WE_O),
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.wbm_cab_o(CAB_O),
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.wbm_cti_o(CTI_O),
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.wbm_bte_o(BTE_O),
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.wbm_ack_i(ACK_I),
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.wbm_ack_i(ACK_I),
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.wbm_rty_i(RTY_I),
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.wbm_rty_i(RTY_I),
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.wbm_err_i(ERR_I),
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.wbm_err_i(ERR_I),
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// pci interface - system pins
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// pci interface - system pins
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