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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/08/09 14:42:34 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// Changed files during testing
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// New project directory structure
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//
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// Revision 1.1 2001/08/06 18:12:43 mihad
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// Pocasi delamo kompletno zadevo
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//
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//
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//
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// FIFO parameters define behaviour of FIFO control logic and ////
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//// FIFO parameters define behaviour of FIFO control logic and ////
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// 8) depth for each FIFO. FIFO depth MUST be power of 2, so address length can
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// 8) depth for each FIFO. FIFO depth MUST be power of 2, so address length can
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// be defined
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// be defined
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// Minimum FIFO depth of any FIFO is 8 - control logic is such that address
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// Minimum FIFO depth of any FIFO is 8 - control logic is such that address
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// lengths less than 3 are not supported
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// lengths less than 3 are not supported
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`define FPGA
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`define FPGA
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`define WBW_DEPTH 32
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`define WBW_DEPTH 16
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`define WBW_ADDR_LENGTH 4
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`define WBW_ADDR_LENGTH 4
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`define WBR_DEPTH 32
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`define WBR_DEPTH 32
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`define WBR_ADDR_LENGTH 5
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`define WBR_ADDR_LENGTH 5
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`define PCIW_DEPTH 32
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`define PCIW_DEPTH 32
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`define PCIW_ADDR_LENGTH 6
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`define PCIW_ADDR_LENGTH 5
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`define PCIR_DEPTH 32
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`define PCIR_DEPTH 32
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`define PCIR_ADDR_LENGTH 7
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`define PCIR_ADDR_LENGTH 5
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//`define BIG
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//`define BIG
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// if FPGA is not defined (commented out), there can still be control logic
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// if FPGA is not defined (commented out), there can still be control logic
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// for synchronous rams used by defining SYNCHRONOUS
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// for synchronous rams used by defining SYNCHRONOUS
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`define SYNCHRONOUS
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`define SYNCHRONOUS
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`timescale 1ns/10ps
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`timescale 1ns/10ps
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// PCI bridge HOST/GUEST implentation
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// PCI bridge HOST/GUEST implentation
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// - for HOST implementation 'HOST' MUST be written othervise there is GUEST
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// - for HOST implementation 'HOST' MUST be written othervise there is GUEST
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// implementation and 'GUEST MUST be written !!!
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// implementation and 'GUEST MUST be written !!!
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`define GUEST
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`define HOST
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// MAX Retry counter value for WISHBONE Master state-machine
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// MAX Retry counter value for WISHBONE Master state-machine
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// This value is 8-bit because of 8-bit retry counter !!!
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// This value is 8-bit because of 8-bit retry counter !!!
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`define WB_RTY_CNT_MAX 8'hff
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`define WB_RTY_CNT_MAX 8'hff
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// the maximum number of images.
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// the maximum number of images.
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// There is one exeption, when the core is implemented as HOST. If so, then the
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// There is one exeption, when the core is implemented as HOST. If so, then the
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// PCI specification allowes the Configuration space NOT to be visible on the
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// PCI specification allowes the Configuration space NOT to be visible on the
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// PCI bus. With `define PCI_IMAGE6 (and `define HOST), we assign PCI_IMAGE0
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// PCI bus. With `define PCI_IMAGE6 (and `define HOST), we assign PCI_IMAGE0
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// to normal WB to PCI image and not to configuration space!
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// to normal WB to PCI image and not to configuration space!
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`define PCI_IMAGE3
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`define PCI_IMAGE6
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`define PCI_AM0 20'hfff0_0
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`define PCI_AM0 20'hffff_f
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`define PCI_AM1 20'hfff0_0
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`define PCI_AM1 20'hffff_f
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`define PCI_AM2 20'h0000_0
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`define PCI_AM2 20'hffff_f
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`define PCI_AM3 20'h0000_0
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`define PCI_AM3 20'hffff_f
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`define PCI_AM4 20'h0000_0
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`define PCI_AM4 20'hffff_f
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`define PCI_AM5 20'h0000_0
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`define PCI_AM5 20'hffff_f
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// no. of WISHBONE Slave IMAGES
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// no. of WISHBONE Slave IMAGES
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// - The maximum number of images is "6". By default there are first two images
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// - The maximum number of images is "6". By default there are first two images
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// used and the first (WB_IMAGE0) is assigned to Configuration space! With a
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// used and the first (WB_IMAGE0) is assigned to Configuration space! With a
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// 'define' WB_IMAGEx you choose the number of used WB IMAGES in a bridge
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// 'define' WB_IMAGEx you choose the number of used WB IMAGES in a bridge
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// without WB_IMAGE0 (e.g. WB_IMAGE3 tells, that WB_IMAGE1, WB_IMAGE2 and
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// without WB_IMAGE0 (e.g. WB_IMAGE3 tells, that WB_IMAGE1, WB_IMAGE2 and
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// WB_IMAGE3 are used for mapping the space from PCI to WB. Offcourse,
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// WB_IMAGE3 are used for mapping the space from PCI to WB. Offcourse,
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// WB_IMAGE0 is assigned to Configuration space). That leave us WB_IMAGE5 as
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// WB_IMAGE0 is assigned to Configuration space). That leave us WB_IMAGE5 as
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// the maximum number of images.
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// the maximum number of images.
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`define WB_IMAGE5
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`define WB_IMAGE5
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`define WB_AM0 20'hffff_f
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// if WB_CNF_IMAGE is commented out, than access to configuration space from WISHBONE for GUEST bridges is disabled alltogether ( even read only )
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// if WB_CNF_IMAGE is commented out, than access to configuration space from WISHBONE for GUEST bridges is disabled alltogether ( even read only )
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//`define WB_CNF_IMAGE
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//`define WB_CNF_IMAGE
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// decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
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// decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
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// slower the decode speed, faster the WISHBONE clock can be
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// slower the decode speed, faster the WISHBONE clock can be
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//`define WB_DECODE_FAST
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`define WB_DECODE_FAST
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`define WB_DECODE_MEDIUM
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//`define WB_DECODE_MEDIUM
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//`define WB_DECODE_SLOW
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//`define WB_DECODE_SLOW
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// definition of how many address lines are compared on address decoding for WISHBONE and PCI images. Put a number of smallest image used here.
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// definition of how many address lines are compared on address decoding for WISHBONE and PCI images. Put a number of smallest image used here.
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// Minimum number is 1 and maximum number is 20 ( 1 = only 2GB images can be done, 20 - 4KB image is smallest possible)
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// Minimum number is 1 and maximum number is 20 ( 1 = only 2GB images can be done, 20 - 4KB image is smallest possible)
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`define WB_NUM_OF_DEC_ADDR_LINES 20
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`define WB_NUM_OF_DEC_ADDR_LINES 20
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