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#-- Synplicity, Inc.
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#-- Synplicity, Inc.
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#-- Version 7.2
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#-- Version 7.3.4
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#-- Project file /shared/projects/pci/mihad/pci/apps/test/syn/synplify/pci_test_top.prj
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#-- Project file /shared/projects/pci/mihad/pci_new_bist/apps/test/syn/synplify/pci_test_top.prj
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#-- Written on Tue Jul 29 12:49:45 2003
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#-- Written on Tue Dec 16 12:47:51 2003
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#add_file options
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#add_file options
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add_file -verilog "$LIB/xilinx/virtex.v"
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add_file -verilog "$LIB/xilinx/virtex.v"
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add_file -verilog "../../../../rtl/verilog/meta_flop.v"
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add_file -verilog "../../../../rtl/verilog/pci_async_reset_flop.v"
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add_file -verilog "../../../../rtl/verilog/pci_async_reset_flop.v"
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add_file -verilog "../../rtl/verilog/pci_bridge32.v"
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add_file -verilog "../../rtl/verilog/pci_bridge32.v"
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add_file -verilog "../../../../rtl/verilog/pci_cbe_en_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_cbe_en_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_conf_cyc_addr_dec.v"
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add_file -verilog "../../../../rtl/verilog/pci_conf_cyc_addr_dec.v"
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add_file -verilog "../../../../rtl/verilog/pci_conf_space.v"
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add_file -verilog "../../../../rtl/verilog/pci_conf_space.v"
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add_file -verilog "../../../../rtl/verilog/pci_wb_slave_unit.v"
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add_file -verilog "../../../../rtl/verilog/pci_wb_slave_unit.v"
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add_file -verilog "../../../../rtl/verilog/pci_wb_slave.v"
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add_file -verilog "../../../../rtl/verilog/pci_wb_slave.v"
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add_file -verilog "../../../../rtl/verilog/pci_wb_tpram.v"
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add_file -verilog "../../../../rtl/verilog/pci_wb_tpram.v"
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add_file -verilog "../../../../rtl/verilog/pci_wbw_fifo_control.v"
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add_file -verilog "../../../../rtl/verilog/pci_wbw_fifo_control.v"
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add_file -verilog "../../../../rtl/verilog/pci_wbw_wbr_fifos.v"
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add_file -verilog "../../../../rtl/verilog/pci_wbw_wbr_fifos.v"
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add_file -verilog "../../../../rtl/verilog/synchronizer_flop.v"
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add_file -verilog "../../../../rtl/verilog/pci_synchronizer_flop.v"
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add_file -constraint "pci_test_top_2clks.sdc"
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add_file -verilog "../../../../rtl/verilog/pci_wbs_wbb3_2_wbb2.v"
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add_file -verilog "../../rtl/verilog/test.v"
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add_file -verilog "../../rtl/verilog/test.v"
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add_file -verilog "../../rtl/verilog/pci_test_top_2clks.v"
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add_file -verilog "../../rtl/verilog/pci_test_top_2clks.v"
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add_file -constraint "pci_test_top_2clks.sdc"
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#implementation: "rev_1"
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#implementation: "rev_1"
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impl -add rev_1
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impl -add rev_1
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#device options
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#device options
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set_option -technology SPARTAN2
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set_option -technology SPARTAN2
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set_option -part XC2S150
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set_option -part XC2S200
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set_option -package PQ208
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set_option -package PQ208
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set_option -speed_grade -5
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set_option -speed_grade -6
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#compilation/mapping options
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#compilation/mapping options
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set_option -default_enum_encoding default
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set_option -default_enum_encoding default
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set_option -symbolic_fsm_compiler 0
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set_option -symbolic_fsm_compiler 0
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set_option -resource_sharing 1
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set_option -resource_sharing 1
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#map options
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#map options
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set_option -frequency 50.000
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set_option -frequency 50.000
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set_option -fanout_limit 16
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set_option -fanout_limit 16
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set_option -disable_io_insertion 0
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set_option -disable_io_insertion 0
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set_option -pipe 0
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set_option -pipe 0
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set_option -fixgatedclocks 0
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set_option -retiming 0
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set_option -retiming 0
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set_option -modular 0
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set_option -modular 0
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set_option -update_models_cp 0
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set_option -update_models_cp 0
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set_option -verification_mode 0
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set_option -verification_mode 0
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#set result format/file last
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#set result format/file last
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project -result_file "rev_1/pci_test_top.edf"
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project -result_file "rev_1/pci_test_top.edf"
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#implementation attributes
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#implementation attributes
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set_option -vlog_std v2001
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set_option -vlog_std v2001
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set_option -compiler_compatible 0
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#implementation attributes
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set_option -random_floorplan 0
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set_option -random_floorplan 0
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set_option -popfeed 1
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set_option -popfeed 1
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set_option -constprop 1
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set_option -constprop 1
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set_option -createhierarchy 0
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set_option -createhierarchy 0
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set_option -floorplan ""
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set_option -floorplan ""
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