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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/02/01 14:43:31 mihad
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// *** empty log message ***
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//
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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// New project directory structure
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// PCI target & WB slave ADDRESS names for configuration space !!!
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// PCI target & WB slave ADDRESS names for configuration space !!!
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// This does not include address offsets of PCI Header registers - they starts at offset 0 (see PCI spec.)
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// This does not include address offsets of PCI Header registers - they starts at offset 0 (see PCI spec.)
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// ALL VALUES are without 2 LSBits AND there is required that address bit [8] is set while
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// ALL VALUES are without 2 LSBits AND there is required that address bit [8] is set while
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// accessing this registers, otherwise the configuration header will be accessed !!!
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// accessing this registers, otherwise the configuration header will be accessed !!!
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`define PCI_CAP_PTR_VAL 8'h80
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`define P_IMG_CTRL0_ADDR 6'h00 // Address offset = h 100
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`define P_IMG_CTRL0_ADDR 6'h00 // Address offset = h 100
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`define P_BA0_ADDR 6'h01 // Address offset = h 104
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`define P_BA0_ADDR 6'h01 // Address offset = h 104
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`define P_AM0_ADDR 6'h02 // Address offset = h 108
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`define P_AM0_ADDR 6'h02 // Address offset = h 108
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`define P_TA0_ADDR 6'h03 // Address offset = h 10c
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`define P_TA0_ADDR 6'h03 // Address offset = h 10c
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`define P_IMG_CTRL1_ADDR 6'h04 // Address offset = h 110
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`define P_IMG_CTRL1_ADDR 6'h04 // Address offset = h 110
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