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[/] [pci/] [trunk/] [rtl/] [verilog/] [pci_target32_trdy_crit.v] - Diff between revs 21 and 77
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Rev 77 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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// New project directory structure
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module PCI_TARGET32_TRDY_CRIT
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module pci_target32_trdy_crit
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(
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(
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trdy_w,
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trdy_w,
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trdy_w_frm,
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trdy_w_frm,
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trdy_w_frm_irdy,
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trdy_w_frm_irdy,
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pci_frame_in,
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pci_frame_in,
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// PCI trdy output with preserved hierarchy for minimum delay!
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// PCI trdy output with preserved hierarchy for minimum delay!
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assign pci_trdy_out = ~(trdy_w || (trdy_w_frm && ~pci_frame_in) || (trdy_w_frm_irdy && ~pci_frame_in && pci_irdy_in)) ;
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assign pci_trdy_out = ~(trdy_w || (trdy_w_frm && ~pci_frame_in) || (trdy_w_frm_irdy && ~pci_frame_in && pci_irdy_in)) ;
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endmodule
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endmodule
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