| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.2 2003/01/30 22:01:09 mihad
|
|
// Updated synchronization in top level fifo modules.
|
|
//
|
// Revision 1.1 2003/01/27 16:49:31 mihad
|
// Revision 1.1 2003/01/27 16:49:31 mihad
|
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
|
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
|
//
|
//
|
// Revision 1.7 2002/12/05 12:19:23 mihad
|
// Revision 1.7 2002/12/05 12:19:23 mihad
|
// *** empty log message ***
|
// *** empty log message ***
|
| Line 365... |
Line 368... |
last_data_to_pcir_fifo = 1'b1 ;
|
last_data_to_pcir_fifo = 1'b1 ;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
|
reg wait_for_wb_response ;
|
|
|
|
`ifdef PCI_WBM_NO_RESPONSE_CNT_DISABLE
|
|
wire set_retry = 1'b0 ;
|
|
|
|
`else
|
reg [3:0] wb_no_response_cnt ;
|
reg [3:0] wb_no_response_cnt ;
|
reg [3:0] wb_response_value ;
|
reg [3:0] wb_response_value ;
|
reg wait_for_wb_response ;
|
|
reg set_retry ; //
|
reg set_retry ; //
|
|
|
// internal WB no response retry generator counter!
|
// internal WB no response retry generator counter!
|
always@(posedge reset_in or posedge wb_clock_in)
|
always@(posedge reset_in or posedge wb_clock_in)
|
begin
|
begin
|
| Line 395... |
Line 403... |
else
|
else
|
wb_response_value = 4'h0 ;
|
wb_response_value = 4'h0 ;
|
set_retry = 1'b0 ;
|
set_retry = 1'b0 ;
|
end
|
end
|
end
|
end
|
|
`endif
|
|
|
wire retry = RTY_I || set_retry ; // retry signal - logic OR function between RTY_I and internal WB no response retry!
|
wire retry = RTY_I || set_retry ; // retry signal - logic OR function between RTY_I and internal WB no response retry!
|
reg [7:0] rty_counter ; // output from retry counter
|
reg [7:0] rty_counter ; // output from retry counter
|
reg [7:0] rty_counter_in ; // input value - output value + 1 OR output value
|
reg [7:0] rty_counter_in ; // input value - output value + 1 OR output value
|
reg rty_counter_almost_max_value ; // signal tells when retry counter riches maximum value - 1!
|
reg rty_counter_almost_max_value ; // signal tells when retry counter riches maximum value - 1!
|
| Line 608... |
Line 617... |
retried_d = 1'b0 ;
|
retried_d = 1'b0 ;
|
last_data_transferred = 1'b0 ;
|
last_data_transferred = 1'b0 ;
|
wb_read_done = 1'b0 ;
|
wb_read_done = 1'b0 ;
|
wait_for_wb_response = 1'b0 ;
|
wait_for_wb_response = 1'b0 ;
|
write_rty_cnt_exp_out = 1'b0 ;
|
write_rty_cnt_exp_out = 1'b0 ;
|
error_source_out = 1'b0 ;
|
|
pci_error_sig_out = 1'b0 ;
|
pci_error_sig_out = 1'b0 ;
|
read_rty_cnt_exp_out = 1'b0 ;
|
read_rty_cnt_exp_out = 1'b0 ;
|
case ({w_attempt, r_attempt, retried})
|
case ({w_attempt, r_attempt, retried})
|
3'b101 : // Write request for PCIW_FIFO to WB bus transaction
|
3'b101 : // Write request for PCIW_FIFO to WB bus transaction
|
begin // If there was retry, the same transaction must be initiated
|
begin // If there was retry, the same transaction must be initiated
|
