| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2003/10/17 09:11:52 markom
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// mbist signals updated according to newest convention
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//
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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//
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// Revision 1.8 2002/10/18 03:36:37 tadejm
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// Revision 1.8 2002/10/18 03:36:37 tadejm
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// Changed wrong signal name mbist_sen into mbist_ctrl_i.
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// Changed wrong signal name mbist_sen into mbist_ctrl_i.
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| Line 121... |
Line 124... |
wbu_ta4_in,
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wbu_ta4_in,
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wbu_ta5_in,
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wbu_ta5_in,
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wbu_at_en_in,
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wbu_at_en_in,
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wbu_ccyc_addr_in ,
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wbu_ccyc_addr_in ,
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wbu_master_enable_in,
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wbu_master_enable_in,
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wb_init_complete_in,
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wbu_cache_line_size_not_zero,
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wbu_cache_line_size_not_zero,
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wbu_cache_line_size_in,
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wbu_cache_line_size_in,
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wbu_pciif_gnt_in,
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wbu_pciif_gnt_in,
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wbu_pciif_frame_in,
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wbu_pciif_frame_in,
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wbu_pciif_irdy_in,
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wbu_pciif_irdy_in,
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| Line 221... |
Line 225... |
input [5:0] wbu_at_en_in ;
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input [5:0] wbu_at_en_in ;
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input [23:0] wbu_ccyc_addr_in ;
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input [23:0] wbu_ccyc_addr_in ;
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input wbu_master_enable_in ;
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input wbu_master_enable_in ;
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input wb_init_complete_in ;
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input wbu_cache_line_size_not_zero ;
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input wbu_cache_line_size_not_zero ;
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input [7:0] wbu_cache_line_size_in ;
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input [7:0] wbu_cache_line_size_in ;
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input wbu_pciif_gnt_in ;
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input wbu_pciif_gnt_in ;
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| Line 471... |
Line 476... |
wire wbs_sm_we_in = WE_I ;
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wire wbs_sm_we_in = WE_I ;
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wire [3:0] wbs_sm_sel_in = SEL_I ;
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wire [3:0] wbs_sm_sel_in = SEL_I ;
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wire [31:0] wbs_sm_sdata_in = SDATA_I ;
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wire [31:0] wbs_sm_sdata_in = SDATA_I ;
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wire wbs_sm_cab_in = CAB_I ;
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wire wbs_sm_cab_in = CAB_I ;
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wire [31:0] wbs_sm_ccyc_addr_in = ccyc_addr_out ;
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wire [31:0] wbs_sm_ccyc_addr_in = ccyc_addr_out ;
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wire wbs_sm_init_complete_in = wb_init_complete_in ;
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// WISHBONE slave interface instantiation
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// WISHBONE slave interface instantiation
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pci_wb_slave wishbone_slave(
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pci_wb_slave wishbone_slave(
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.wb_clock_in (wb_clock_in) ,
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.wb_clock_in (wb_clock_in) ,
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.reset_in (reset_in) ,
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.reset_in (reset_in) ,
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| Line 515... |
Line 521... |
.wbr_fifo_control_in (wbs_sm_wbr_control_in),
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.wbr_fifo_control_in (wbs_sm_wbr_control_in),
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.wbr_fifo_flush_out (wbs_sm_wbr_flush_out),
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.wbr_fifo_flush_out (wbs_sm_wbr_flush_out),
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.wbr_fifo_empty_in (wbs_sm_wbr_empty_in),
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.wbr_fifo_empty_in (wbs_sm_wbr_empty_in),
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.pciw_fifo_empty_in (wbs_sm_pciw_empty_in),
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.pciw_fifo_empty_in (wbs_sm_pciw_empty_in),
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.wbs_lock_in (wbs_sm_lock_in),
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.wbs_lock_in (wbs_sm_lock_in),
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.init_complete_in (wbs_sm_init_complete_in),
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.cache_line_size_not_zero (wbs_sm_cache_line_size_not_zero),
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.cache_line_size_not_zero (wbs_sm_cache_line_size_not_zero),
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.del_in_progress_out (wbs_sm_del_in_progress_out),
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.del_in_progress_out (wbs_sm_del_in_progress_out),
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.ccyc_addr_in (wbs_sm_ccyc_addr_in),
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.ccyc_addr_in (wbs_sm_ccyc_addr_in),
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.sample_address_out (wbs_sm_sample_address_out),
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.sample_address_out (wbs_sm_sample_address_out),
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.CYC_I (wbs_sm_cyc_in),
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.CYC_I (wbs_sm_cyc_in),
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