OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [trunk/] [rtl/] [verilog/] [pci_wb_slave_unit.v] - Diff between revs 140 and 153

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 140 Rev 153
Line 40... Line 40...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.3  2004/01/24 11:54:18  mihad
 
// Update! SPOCI Implemented!
 
//
// Revision 1.2  2003/10/17 09:11:52  markom
// Revision 1.2  2003/10/17 09:11:52  markom
// mbist signals updated according to newest convention
// mbist signals updated according to newest convention
//
//
// Revision 1.1  2003/01/27 16:49:31  mihad
// Revision 1.1  2003/01/27 16:49:31  mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
Line 409... Line 412...
wire [31:0] fifos_wbw_addr_data_out ;
wire [31:0] fifos_wbw_addr_data_out ;
wire [3:0]  fifos_wbw_cbe_out ;
wire [3:0]  fifos_wbw_cbe_out ;
wire [3:0]  fifos_wbw_control_out ;
wire [3:0]  fifos_wbw_control_out ;
wire        fifos_wbw_almost_full_out ;
wire        fifos_wbw_almost_full_out ;
wire        fifos_wbw_full_out ;
wire        fifos_wbw_full_out ;
 
wire        fifos_wbw_half_full_out; //Robert, burst issue
wire        fifos_wbw_empty_out ;
wire        fifos_wbw_empty_out ;
wire        fifos_wbw_transaction_ready_out ;
wire        fifos_wbw_transaction_ready_out ;
 
 
// wbr_fifo_outputs
// wbr_fifo_outputs
wire [31:0] fifos_wbr_data_out ;
wire [31:0] fifos_wbr_data_out ;
Line 462... Line 466...
wire [31:0] wbs_sm_del_addr_in              =       del_sync_addr_out ;
wire [31:0] wbs_sm_del_addr_in              =       del_sync_addr_out ;
wire [3:0]  wbs_sm_del_be_in                =       del_sync_be_out ;
wire [3:0]  wbs_sm_del_be_in                =       del_sync_be_out ;
wire [31:0] wbs_sm_conf_data_in             =       wbu_conf_data_in ;
wire [31:0] wbs_sm_conf_data_in             =       wbu_conf_data_in ;
wire        wbs_sm_wbw_almost_full_in       =       fifos_wbw_almost_full_out ;
wire        wbs_sm_wbw_almost_full_in       =       fifos_wbw_almost_full_out ;
wire        wbs_sm_wbw_full_in              =       fifos_wbw_full_out ;
wire        wbs_sm_wbw_full_in              =       fifos_wbw_full_out ;
 
wire        wbs_sm_wbw_half_full_in         =       fifos_wbw_half_full_out; ////Robert, burst issue
wire [3:0]  wbs_sm_wbr_be_in                =       fifos_wbr_be_out ;
wire [3:0]  wbs_sm_wbr_be_in                =       fifos_wbr_be_out ;
wire [31:0] wbs_sm_wbr_data_in              =       fifos_wbr_data_out ;
wire [31:0] wbs_sm_wbr_data_in              =       fifos_wbr_data_out ;
wire [3:0]  wbs_sm_wbr_control_in           =       fifos_wbr_control_out ;
wire [3:0]  wbs_sm_wbr_control_in           =       fifos_wbr_control_out ;
wire        wbs_sm_wbr_empty_in             =       fifos_wbr_empty_out ;
wire        wbs_sm_wbr_empty_in             =       fifos_wbr_empty_out ;
wire        wbs_sm_pciw_empty_in            =       wbu_pciw_empty_in ;
wire        wbs_sm_pciw_empty_in            =       wbu_pciw_empty_in ;
Line 513... Line 518...
                        .wb_cbe_out               (wbs_sm_cbe_out),
                        .wb_cbe_out               (wbs_sm_cbe_out),
                        .wbw_fifo_wenable_out     (wbs_sm_wbw_wenable_out),
                        .wbw_fifo_wenable_out     (wbs_sm_wbw_wenable_out),
                        .wbw_fifo_control_out     (wbs_sm_wbw_control_out),
                        .wbw_fifo_control_out     (wbs_sm_wbw_control_out),
                        .wbw_fifo_almost_full_in  (wbs_sm_wbw_almost_full_in),
                        .wbw_fifo_almost_full_in  (wbs_sm_wbw_almost_full_in),
                        .wbw_fifo_full_in         (wbs_sm_wbw_full_in),
                        .wbw_fifo_full_in         (wbs_sm_wbw_full_in),
 
                                                                .wbw_fifo_half_full_in    (wbs_sm_wbw_half_full_in), ////Robert, burst issue
                        .wbr_fifo_renable_out     (wbs_sm_wbr_renable_out),
                        .wbr_fifo_renable_out     (wbs_sm_wbr_renable_out),
                        .wbr_fifo_be_in           (wbs_sm_wbr_be_in),
                        .wbr_fifo_be_in           (wbs_sm_wbr_be_in),
                        .wbr_fifo_data_in         (wbs_sm_wbr_data_in),
                        .wbr_fifo_data_in         (wbs_sm_wbr_data_in),
                        .wbr_fifo_control_in      (wbs_sm_wbr_control_in),
                        .wbr_fifo_control_in      (wbs_sm_wbr_control_in),
                        .wbr_fifo_flush_out       (wbs_sm_wbr_flush_out),
                        .wbr_fifo_flush_out       (wbs_sm_wbr_flush_out),
Line 575... Line 581...
//    .wbw_flush_in              (fifos_wbw_flush_in),        // flush for write fifo not used
//    .wbw_flush_in              (fifos_wbw_flush_in),        // flush for write fifo not used
    .wbw_almost_full_out       (fifos_wbw_almost_full_out),
    .wbw_almost_full_out       (fifos_wbw_almost_full_out),
    .wbw_full_out              (fifos_wbw_full_out),
    .wbw_full_out              (fifos_wbw_full_out),
    .wbw_empty_out             (fifos_wbw_empty_out),
    .wbw_empty_out             (fifos_wbw_empty_out),
    .wbw_transaction_ready_out (fifos_wbw_transaction_ready_out),
    .wbw_transaction_ready_out (fifos_wbw_transaction_ready_out),
 
         .wbw_half_full_out        (fifos_wbw_half_full_out),////Robert, burst issue
    .wbr_wenable_in            (fifos_wbr_wenable_in),
    .wbr_wenable_in            (fifos_wbr_wenable_in),
    .wbr_data_in               (fifos_wbr_data_in),
    .wbr_data_in               (fifos_wbr_data_in),
    .wbr_be_in                 (fifos_wbr_be_in),
    .wbr_be_in                 (fifos_wbr_be_in),
    .wbr_control_in            (fifos_wbr_control_in),
    .wbr_control_in            (fifos_wbr_control_in),
    .wbr_renable_in            (fifos_wbr_renable_in),
    .wbr_renable_in            (fifos_wbr_renable_in),

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.