Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2004/01/24 11:54:18 mihad
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// Update! SPOCI Implemented!
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//
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// Revision 1.2 2003/10/17 09:11:52 markom
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// Revision 1.2 2003/10/17 09:11:52 markom
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// mbist signals updated according to newest convention
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// mbist signals updated according to newest convention
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//
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//
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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Line 409... |
Line 412... |
wire [31:0] fifos_wbw_addr_data_out ;
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wire [31:0] fifos_wbw_addr_data_out ;
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wire [3:0] fifos_wbw_cbe_out ;
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wire [3:0] fifos_wbw_cbe_out ;
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wire [3:0] fifos_wbw_control_out ;
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wire [3:0] fifos_wbw_control_out ;
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wire fifos_wbw_almost_full_out ;
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wire fifos_wbw_almost_full_out ;
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wire fifos_wbw_full_out ;
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wire fifos_wbw_full_out ;
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wire fifos_wbw_half_full_out; //Robert, burst issue
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wire fifos_wbw_empty_out ;
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wire fifos_wbw_empty_out ;
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wire fifos_wbw_transaction_ready_out ;
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wire fifos_wbw_transaction_ready_out ;
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// wbr_fifo_outputs
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// wbr_fifo_outputs
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wire [31:0] fifos_wbr_data_out ;
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wire [31:0] fifos_wbr_data_out ;
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Line 462... |
Line 466... |
wire [31:0] wbs_sm_del_addr_in = del_sync_addr_out ;
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wire [31:0] wbs_sm_del_addr_in = del_sync_addr_out ;
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wire [3:0] wbs_sm_del_be_in = del_sync_be_out ;
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wire [3:0] wbs_sm_del_be_in = del_sync_be_out ;
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wire [31:0] wbs_sm_conf_data_in = wbu_conf_data_in ;
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wire [31:0] wbs_sm_conf_data_in = wbu_conf_data_in ;
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wire wbs_sm_wbw_almost_full_in = fifos_wbw_almost_full_out ;
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wire wbs_sm_wbw_almost_full_in = fifos_wbw_almost_full_out ;
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wire wbs_sm_wbw_full_in = fifos_wbw_full_out ;
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wire wbs_sm_wbw_full_in = fifos_wbw_full_out ;
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wire wbs_sm_wbw_half_full_in = fifos_wbw_half_full_out; ////Robert, burst issue
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wire [3:0] wbs_sm_wbr_be_in = fifos_wbr_be_out ;
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wire [3:0] wbs_sm_wbr_be_in = fifos_wbr_be_out ;
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wire [31:0] wbs_sm_wbr_data_in = fifos_wbr_data_out ;
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wire [31:0] wbs_sm_wbr_data_in = fifos_wbr_data_out ;
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wire [3:0] wbs_sm_wbr_control_in = fifos_wbr_control_out ;
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wire [3:0] wbs_sm_wbr_control_in = fifos_wbr_control_out ;
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wire wbs_sm_wbr_empty_in = fifos_wbr_empty_out ;
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wire wbs_sm_wbr_empty_in = fifos_wbr_empty_out ;
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wire wbs_sm_pciw_empty_in = wbu_pciw_empty_in ;
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wire wbs_sm_pciw_empty_in = wbu_pciw_empty_in ;
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Line 513... |
Line 518... |
.wb_cbe_out (wbs_sm_cbe_out),
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.wb_cbe_out (wbs_sm_cbe_out),
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.wbw_fifo_wenable_out (wbs_sm_wbw_wenable_out),
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.wbw_fifo_wenable_out (wbs_sm_wbw_wenable_out),
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.wbw_fifo_control_out (wbs_sm_wbw_control_out),
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.wbw_fifo_control_out (wbs_sm_wbw_control_out),
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.wbw_fifo_almost_full_in (wbs_sm_wbw_almost_full_in),
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.wbw_fifo_almost_full_in (wbs_sm_wbw_almost_full_in),
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.wbw_fifo_full_in (wbs_sm_wbw_full_in),
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.wbw_fifo_full_in (wbs_sm_wbw_full_in),
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.wbw_fifo_half_full_in (wbs_sm_wbw_half_full_in), ////Robert, burst issue
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.wbr_fifo_renable_out (wbs_sm_wbr_renable_out),
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.wbr_fifo_renable_out (wbs_sm_wbr_renable_out),
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.wbr_fifo_be_in (wbs_sm_wbr_be_in),
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.wbr_fifo_be_in (wbs_sm_wbr_be_in),
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.wbr_fifo_data_in (wbs_sm_wbr_data_in),
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.wbr_fifo_data_in (wbs_sm_wbr_data_in),
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.wbr_fifo_control_in (wbs_sm_wbr_control_in),
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.wbr_fifo_control_in (wbs_sm_wbr_control_in),
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.wbr_fifo_flush_out (wbs_sm_wbr_flush_out),
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.wbr_fifo_flush_out (wbs_sm_wbr_flush_out),
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Line 575... |
Line 581... |
// .wbw_flush_in (fifos_wbw_flush_in), // flush for write fifo not used
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// .wbw_flush_in (fifos_wbw_flush_in), // flush for write fifo not used
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.wbw_almost_full_out (fifos_wbw_almost_full_out),
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.wbw_almost_full_out (fifos_wbw_almost_full_out),
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.wbw_full_out (fifos_wbw_full_out),
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.wbw_full_out (fifos_wbw_full_out),
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.wbw_empty_out (fifos_wbw_empty_out),
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.wbw_empty_out (fifos_wbw_empty_out),
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.wbw_transaction_ready_out (fifos_wbw_transaction_ready_out),
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.wbw_transaction_ready_out (fifos_wbw_transaction_ready_out),
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.wbw_half_full_out (fifos_wbw_half_full_out),////Robert, burst issue
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.wbr_wenable_in (fifos_wbr_wenable_in),
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.wbr_wenable_in (fifos_wbr_wenable_in),
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.wbr_data_in (fifos_wbr_data_in),
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.wbr_data_in (fifos_wbr_data_in),
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.wbr_be_in (fifos_wbr_be_in),
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.wbr_be_in (fifos_wbr_be_in),
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.wbr_control_in (fifos_wbr_control_in),
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.wbr_control_in (fifos_wbr_control_in),
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.wbr_renable_in (fifos_wbr_renable_in),
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.wbr_renable_in (fifos_wbr_renable_in),
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