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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2003/08/14 13:06:03 simons
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// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.
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//
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// Revision 1.3 2003/07/29 08:20:11 mihad
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// Revision 1.3 2003/07/29 08:20:11 mihad
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// Found and simulated the problem in the synchronization logic.
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// Found and simulated the problem in the synchronization logic.
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// Repaired the synchronization logic in the FIFOs.
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// Repaired the synchronization logic in the FIFOs.
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//
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//
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// Revision 1.2 2003/03/26 13:16:18 mihad
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// Revision 1.2 2003/03/26 13:16:18 mihad
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full_out,
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full_out,
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empty_out,
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empty_out,
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waddr_out,
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waddr_out,
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raddr_out,
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raddr_out,
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rallow_out,
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rallow_out,
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wallow_out
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wallow_out,
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half_full_out ////Robert, burst issue
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);
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);
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parameter ADDR_LENGTH = 7 ;
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parameter ADDR_LENGTH = 7 ;
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// independent clock inputs - rclock_in = read clock, wclock_in = write clock
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// independent clock inputs - rclock_in = read clock, wclock_in = write clock
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output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
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output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
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// read and write allow outputs
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// read and write allow outputs
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output rallow_out, wallow_out ;
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output rallow_out, wallow_out ;
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output half_full_out;
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// read address register
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// read address register
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reg [(ADDR_LENGTH - 1):0] raddr ;
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reg [(ADDR_LENGTH - 1):0] raddr ;
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// write address register
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// write address register
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reg [(ADDR_LENGTH - 1):0] waddr;
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reg [(ADDR_LENGTH - 1):0] waddr;
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// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
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// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
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// when FIFO is empty, this register provides actual read address, so first location can be read
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// when FIFO is empty, this register provides actual read address, so first location can be read
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reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
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reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
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wire [ADDR_LENGTH :0] fifo_fullness; //Robert, burst issue
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//Robert, burst issue
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assign fifo_fullness = (waddr > raddr) ? ({1'b0, waddr} - {1'b0, raddr}) : ({1'b1, waddr} - {1'b0, raddr});
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assign half_full_out = fifo_fullness[(ADDR_LENGTH - 1)] ;
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//Robert, burst issue
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// address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out
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// address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out
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// done for zero wait state burst
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// done for zero wait state burst
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assign raddr_out = rallow_out ? raddr_plus_one : raddr ;
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assign raddr_out = rallow_out ? raddr_plus_one : raddr ;
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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