| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2003/12/19 11:11:30 mihad
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// Compact PCI Hot Swap support added.
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// New testcases added.
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// Specification updated.
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// Test application changed to support WB B3 cycles.
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//
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// Revision 1.5 2003/10/17 09:11:52 markom
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// Revision 1.5 2003/10/17 09:11:52 markom
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// mbist signals updated according to newest convention
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// mbist signals updated according to newest convention
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//
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//
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// Revision 1.4 2003/08/14 13:06:03 simons
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// Revision 1.4 2003/08/14 13:06:03 simons
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// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.
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// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.
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| Line 92... |
Line 98... |
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module pci_wbw_wbr_fifos
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module pci_wbw_wbr_fifos
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(
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(
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wb_clock_in,
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wb_clock_in,
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pci_clock_in,
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pci_clock_in,
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reset_in,
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reset_in,
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| Line 110... |
Line 118... |
// wbw_flush_in, write fifo flush not used
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// wbw_flush_in, write fifo flush not used
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wbw_almost_full_out,
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wbw_almost_full_out,
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wbw_full_out,
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wbw_full_out,
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wbw_empty_out,
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wbw_empty_out,
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wbw_transaction_ready_out,
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wbw_transaction_ready_out,
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wbw_half_full_out, ////Robert, burst issue
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wbr_wenable_in,
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wbr_wenable_in,
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wbr_data_in,
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wbr_data_in,
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wbr_be_in,
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wbr_be_in,
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wbr_control_in,
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wbr_control_in,
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wbr_renable_in,
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wbr_renable_in,
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| Line 121... |
Line 130... |
wbr_be_out,
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wbr_be_out,
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wbr_control_out,
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wbr_control_out,
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wbr_flush_in,
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wbr_flush_in,
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wbr_empty_out
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wbr_empty_out
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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// debug chain signals
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// debug chain signals
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mbist_si_i, // bist scan serial in
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mbist_si_i, // bist scan serial in
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mbist_so_o, // bist scan serial out
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mbist_so_o, // bist scan serial out
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| Line 185... |
Line 195... |
// status outputs
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// status outputs
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output wbw_almost_full_out ;
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output wbw_almost_full_out ;
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output wbw_full_out ;
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output wbw_full_out ;
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output wbw_empty_out ;
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output wbw_empty_out ;
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output wbw_transaction_ready_out ;
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output wbw_transaction_ready_out ;
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output wbw_half_full_out; ////Robert, burst issue
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/*-----------------------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------------------
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WISHBONE READ FIFO interface signals prefixed with wbr_ - FIFO is used for holding delayed read completions
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WISHBONE READ FIFO interface signals prefixed with wbr_ - FIFO is used for holding delayed read completions
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initiated by master on WISHBONE bus and completed on PCI bus,
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initiated by master on WISHBONE bus and completed on PCI bus,
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Line 368... |
`endif
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`endif
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// instantiate and connect two generic rams - one for wishbone write fifo and one for wishbone read fifo
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// instantiate and connect two generic rams - one for wishbone write fifo and one for wishbone read fifo
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pci_wb_tpram #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbw_fifo_storage
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pci_wb_tpram #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbw_fifo_storage
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(
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(
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// Generic synchronous two-port RAM interface
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/////////////////Generic synchronous two-port RAM interface
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.clk_a(wb_clock_in),
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.clk_a(wb_clock_in),
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.rst_a(reset_in),
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.rst_a(reset_in),
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.ce_a(1'b1),
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.ce_a(1'b1),
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.we_a(wbw_wallow),
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.we_a(wbw_wallow),
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.oe_a(1'b1),
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.oe_a(1'b1),
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Line 424... |
.mbist_so_o (mbist_so_o),
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.mbist_so_o (mbist_so_o),
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.mbist_ctrl_i (mbist_ctrl_i)
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.mbist_ctrl_i (mbist_ctrl_i)
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`endif
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`endif
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);
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);
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`else // RAM blocks sharing between two fifos
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`else // RAM blocks sharing between two fifos
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/*-----------------------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------------------
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Code section under this ifdef is used for implementation where RAM instances are too expensive. In this
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Code section under this ifdef is used for implementation where RAM instances are too expensive. In this
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case one RAM instance is used for both - WISHBONE read and WISHBONE write fifo.
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case one RAM instance is used for both - WISHBONE read and WISHBONE write fifo.
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| Line 476... |
Line 488... |
`endif
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`endif
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);
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);
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`endif
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`endif
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/*-----------------------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------------------
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Instantiation of two control logic modules - one for WBW_FIFO and one for WBR_FIFO
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Instantiation of two control logic modules - one for WBW_FIFO and one for WBR_FIFO
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-----------------------------------------------------------------------------------------------------------*/
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-----------------------------------------------------------------------------------------------------------*/
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pci_wbw_fifo_control #(WBW_ADDR_LENGTH) wbw_fifo_ctrl
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pci_wbw_fifo_control #(WBW_ADDR_LENGTH) wbw_fifo_ctrl
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(
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(
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.rclock_in(pci_clock_in),
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.rclock_in(pci_clock_in),
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.wclock_in(wb_clock_in),
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.wclock_in(wb_clock_in),
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.renable_in(wbw_renable_in),
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.renable_in(wbw_renable_in),
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.wenable_in(wbw_wenable_in),
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.wenable_in(wbw_wenable_in),
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.reset_in(reset_in),
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.reset_in(reset_in),
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// .flush_in(wbw_flush_in),
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////////////////////////////// .flush_in(wbw_flush_in),
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.almost_full_out(wbw_almost_full_out),
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.almost_full_out(wbw_almost_full_out),
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.full_out(wbw_full_out),
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.full_out(wbw_full_out),
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.empty_out(wbw_empty),
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.empty_out(wbw_empty),
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.waddr_out(wbw_waddr),
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.waddr_out(wbw_waddr),
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.raddr_out(wbw_raddr),
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.raddr_out(wbw_raddr),
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.rallow_out(wbw_rallow),
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.rallow_out(wbw_rallow),
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.wallow_out(wbw_wallow)
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.wallow_out(wbw_wallow),
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.half_full_out(wbw_half_full_out) ////Robert, burst issue
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);
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);
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pci_wbr_fifo_control #(WBR_ADDR_LENGTH) wbr_fifo_ctrl
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pci_wbr_fifo_control #(WBR_ADDR_LENGTH) wbr_fifo_ctrl
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( .rclock_in(wb_clock_in),
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( .rclock_in(wb_clock_in),
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.wclock_in(pci_clock_in),
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.wclock_in(pci_clock_in),
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