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##############################################################
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##############################################################
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#
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#
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# Xilinx Core Generator version 13.2
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# Xilinx Core Generator version 14.5
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# Date: Wed Oct 19 11:25:05 2011
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# Date: Sat Apr 20 16:42:54 2013
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#
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#
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##############################################################
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##############################################################
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#
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#
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# This file contains the customisation parameters for a
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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# unexpected and unsupported behavior.
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#
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#
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##############################################################
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##############################################################
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#
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#
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# Generated from component: xilinx.com:ip:fifo_generator:8.2
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# Generated from component: xilinx.com:ip:fifo_generator:9.3
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#
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#
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##############################################################
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##############################################################
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#
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#
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# BEGIN Project Options
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# BEGIN Project Options
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SET addpads = false
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SET addpads = false
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SET asysymbol = true
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET createndf = false
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SET designentry = VHDL
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SET designentry = VHDL
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SET device = xc6slx45t
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SET device = xc5vsx50t
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SET devicefamily = spartan6
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SET devicefamily = virtex5
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SET flowvendor = Other
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SET flowvendor = Other
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SET formalverification = false
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SET formalverification = false
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SET foundationsym = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET implementationfiletype = Ngc
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SET package = fgg484
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SET package = ff1136
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SET removerpms = false
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SET removerpms = false
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SET simulationfiles = Structural
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SET simulationfiles = Behavioral
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SET speedgrade = -3
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SET speedgrade = -1
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SET verilogsim = false
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SET verilogsim = false
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SET vhdlsim = true
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SET vhdlsim = true
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# END Project Options
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# END Project Options
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# BEGIN Select
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# BEGIN Select
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SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.2
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SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
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# END Select
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# END Select
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# BEGIN Parameters
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# BEGIN Parameters
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CSET add_ngc_constraint_axi=false
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CSET add_ngc_constraint_axi=false
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CSET almost_empty_flag=false
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CSET almost_empty_flag=false
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CSET almost_full_flag=false
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CSET almost_full_flag=false
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| Line 52... |
Line 52... |
CSET clock_enable_type=Slave_Interface_Clock_Enable
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CSET clock_enable_type=Slave_Interface_Clock_Enable
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CSET clock_type_axi=Common_Clock
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CSET clock_type_axi=Common_Clock
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CSET component_name=ctrl_fifo512x64st_v0
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CSET component_name=ctrl_fifo512x64st_v0
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CSET data_count=true
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CSET data_count=true
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CSET data_count_width=9
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CSET data_count_width=9
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CSET disable_timing_violations=false
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CSET disable_timing_violations=true
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CSET disable_timing_violations_axi=false
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CSET disable_timing_violations_axi=false
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CSET dout_reset_value=0
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CSET dout_reset_value=0
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CSET empty_threshold_assert_value=2
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CSET empty_threshold_assert_value=2
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CSET empty_threshold_assert_value_axis=1022
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CSET empty_threshold_assert_value_axis=1022
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CSET empty_threshold_assert_value_rach=1022
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CSET empty_threshold_assert_value_rach=1022
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| Line 81... |
Line 81... |
CSET enable_ecc_rach=false
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CSET enable_ecc_rach=false
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CSET enable_ecc_rdch=false
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CSET enable_ecc_rdch=false
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CSET enable_ecc_wach=false
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CSET enable_ecc_wach=false
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CSET enable_ecc_wdch=false
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CSET enable_ecc_wdch=false
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CSET enable_ecc_wrch=false
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CSET enable_ecc_wrch=false
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CSET enable_handshake_flag_options_axis=false
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CSET enable_handshake_flag_options_rach=false
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CSET enable_handshake_flag_options_rdch=false
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CSET enable_handshake_flag_options_wach=false
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CSET enable_handshake_flag_options_wdch=false
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CSET enable_handshake_flag_options_wrch=false
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CSET enable_read_channel=false
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CSET enable_read_channel=false
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CSET enable_read_pointer_increment_by2=false
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CSET enable_read_pointer_increment_by2=false
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CSET enable_reset_synchronization=true
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CSET enable_reset_synchronization=true
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CSET enable_ruser=false
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CSET enable_ruser=false
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CSET enable_tdata=false
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CSET enable_tdata=false
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Line 149... |
CSET overflow_flag_axi=false
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CSET overflow_flag_axi=false
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CSET overflow_sense=Active_High
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CSET overflow_sense=Active_High
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CSET overflow_sense_axi=Active_High
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CSET overflow_sense_axi=Active_High
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CSET performance_options=Standard_FIFO
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CSET performance_options=Standard_FIFO
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CSET programmable_empty_type=No_Programmable_Empty_Threshold
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CSET programmable_empty_type=No_Programmable_Empty_Threshold
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CSET programmable_empty_type_axis=Empty
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CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
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CSET programmable_empty_type_rach=Empty
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CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
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CSET programmable_empty_type_rdch=Empty
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CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
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CSET programmable_empty_type_wach=Empty
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CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
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CSET programmable_empty_type_wdch=Empty
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CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
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CSET programmable_empty_type_wrch=Empty
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CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
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CSET programmable_full_type=No_Programmable_Full_Threshold
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CSET programmable_full_type=No_Programmable_Full_Threshold
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CSET programmable_full_type_axis=Full
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CSET programmable_full_type_axis=No_Programmable_Full_Threshold
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CSET programmable_full_type_rach=Full
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CSET programmable_full_type_rach=No_Programmable_Full_Threshold
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CSET programmable_full_type_rdch=Full
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CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
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CSET programmable_full_type_wach=Full
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CSET programmable_full_type_wach=No_Programmable_Full_Threshold
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CSET programmable_full_type_wdch=Full
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CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
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CSET programmable_full_type_wrch=Full
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CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
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CSET rach_type=FIFO
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CSET rach_type=FIFO
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CSET rdch_type=FIFO
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CSET rdch_type=FIFO
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CSET read_clock_frequency=1
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CSET read_clock_frequency=1
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CSET read_data_count=false
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CSET read_data_count=false
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CSET read_data_count_width=9
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CSET read_data_count_width=9
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Line 176... |
CSET register_slice_mode_wdch=Fully_Registered
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CSET register_slice_mode_wdch=Fully_Registered
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CSET register_slice_mode_wrch=Fully_Registered
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CSET register_slice_mode_wrch=Fully_Registered
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CSET reset_pin=true
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CSET reset_pin=true
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CSET reset_type=Asynchronous_Reset
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CSET reset_type=Asynchronous_Reset
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CSET ruser_width=1
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CSET ruser_width=1
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CSET synchronization_stages=2
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CSET synchronization_stages_axi=2
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CSET tdata_width=64
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CSET tdata_width=64
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CSET tdest_width=4
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CSET tdest_width=4
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CSET tid_width=8
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CSET tid_width=8
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CSET tkeep_width=4
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CSET tkeep_width=4
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CSET tstrb_width=4
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CSET tstrb_width=4
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Line 205... |
CSET write_data_count=false
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CSET write_data_count=false
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CSET write_data_count_width=9
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CSET write_data_count_width=9
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CSET wuser_width=1
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CSET wuser_width=1
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# END Parameters
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# END Parameters
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# BEGIN Extra information
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# BEGIN Extra information
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MISC pkg_timestamp=2011-03-14T07:12:32.000Z
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MISC pkg_timestamp=2012-11-19T12:39:56Z
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# END Extra information
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# END Extra information
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GENERATE
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GENERATE
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# CRC: c15403dd
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# CRC: e84e4d4d
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# CRC: e84e4d4d
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# CRC: e84e4d4d
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