Line 1... |
Line 1... |
##############################################################
|
##############################################################
|
#
|
#
|
# Xilinx Core Generator version 13.2
|
# Xilinx Core Generator version 14.5
|
# Date: Wed Oct 19 11:25:05 2011
|
# Date: Sat Apr 20 16:42:54 2013
|
#
|
#
|
##############################################################
|
##############################################################
|
#
|
#
|
# This file contains the customisation parameters for a
|
# This file contains the customisation parameters for a
|
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
# that you do not manually alter this file as it may cause
|
# that you do not manually alter this file as it may cause
|
# unexpected and unsupported behavior.
|
# unexpected and unsupported behavior.
|
#
|
#
|
##############################################################
|
##############################################################
|
#
|
#
|
# Generated from component: xilinx.com:ip:fifo_generator:8.2
|
# Generated from component: xilinx.com:ip:fifo_generator:9.3
|
#
|
#
|
##############################################################
|
##############################################################
|
#
|
#
|
# BEGIN Project Options
|
# BEGIN Project Options
|
SET addpads = false
|
SET addpads = false
|
SET asysymbol = true
|
SET asysymbol = true
|
SET busformat = BusFormatAngleBracketNotRipped
|
SET busformat = BusFormatAngleBracketNotRipped
|
SET createndf = false
|
SET createndf = false
|
SET designentry = VHDL
|
SET designentry = VHDL
|
SET device = xc6slx45t
|
SET device = xc5vsx50t
|
SET devicefamily = spartan6
|
SET devicefamily = virtex5
|
SET flowvendor = Other
|
SET flowvendor = Other
|
SET formalverification = false
|
SET formalverification = false
|
SET foundationsym = false
|
SET foundationsym = false
|
SET implementationfiletype = Ngc
|
SET implementationfiletype = Ngc
|
SET package = fgg484
|
SET package = ff1136
|
SET removerpms = false
|
SET removerpms = false
|
SET simulationfiles = Structural
|
SET simulationfiles = Behavioral
|
SET speedgrade = -3
|
SET speedgrade = -1
|
SET verilogsim = false
|
SET verilogsim = false
|
SET vhdlsim = true
|
SET vhdlsim = true
|
# END Project Options
|
# END Project Options
|
# BEGIN Select
|
# BEGIN Select
|
SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.2
|
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
|
# END Select
|
# END Select
|
# BEGIN Parameters
|
# BEGIN Parameters
|
CSET add_ngc_constraint_axi=false
|
CSET add_ngc_constraint_axi=false
|
CSET almost_empty_flag=false
|
CSET almost_empty_flag=false
|
CSET almost_full_flag=false
|
CSET almost_full_flag=false
|
Line 52... |
Line 52... |
CSET clock_enable_type=Slave_Interface_Clock_Enable
|
CSET clock_enable_type=Slave_Interface_Clock_Enable
|
CSET clock_type_axi=Common_Clock
|
CSET clock_type_axi=Common_Clock
|
CSET component_name=ctrl_fifo512x64st_v0
|
CSET component_name=ctrl_fifo512x64st_v0
|
CSET data_count=true
|
CSET data_count=true
|
CSET data_count_width=9
|
CSET data_count_width=9
|
CSET disable_timing_violations=false
|
CSET disable_timing_violations=true
|
CSET disable_timing_violations_axi=false
|
CSET disable_timing_violations_axi=false
|
CSET dout_reset_value=0
|
CSET dout_reset_value=0
|
CSET empty_threshold_assert_value=2
|
CSET empty_threshold_assert_value=2
|
CSET empty_threshold_assert_value_axis=1022
|
CSET empty_threshold_assert_value_axis=1022
|
CSET empty_threshold_assert_value_rach=1022
|
CSET empty_threshold_assert_value_rach=1022
|
Line 81... |
Line 81... |
CSET enable_ecc_rach=false
|
CSET enable_ecc_rach=false
|
CSET enable_ecc_rdch=false
|
CSET enable_ecc_rdch=false
|
CSET enable_ecc_wach=false
|
CSET enable_ecc_wach=false
|
CSET enable_ecc_wdch=false
|
CSET enable_ecc_wdch=false
|
CSET enable_ecc_wrch=false
|
CSET enable_ecc_wrch=false
|
CSET enable_handshake_flag_options_axis=false
|
|
CSET enable_handshake_flag_options_rach=false
|
|
CSET enable_handshake_flag_options_rdch=false
|
|
CSET enable_handshake_flag_options_wach=false
|
|
CSET enable_handshake_flag_options_wdch=false
|
|
CSET enable_handshake_flag_options_wrch=false
|
|
CSET enable_read_channel=false
|
CSET enable_read_channel=false
|
CSET enable_read_pointer_increment_by2=false
|
CSET enable_read_pointer_increment_by2=false
|
CSET enable_reset_synchronization=true
|
CSET enable_reset_synchronization=true
|
CSET enable_ruser=false
|
CSET enable_ruser=false
|
CSET enable_tdata=false
|
CSET enable_tdata=false
|
Line 155... |
Line 149... |
CSET overflow_flag_axi=false
|
CSET overflow_flag_axi=false
|
CSET overflow_sense=Active_High
|
CSET overflow_sense=Active_High
|
CSET overflow_sense_axi=Active_High
|
CSET overflow_sense_axi=Active_High
|
CSET performance_options=Standard_FIFO
|
CSET performance_options=Standard_FIFO
|
CSET programmable_empty_type=No_Programmable_Empty_Threshold
|
CSET programmable_empty_type=No_Programmable_Empty_Threshold
|
CSET programmable_empty_type_axis=Empty
|
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
|
CSET programmable_empty_type_rach=Empty
|
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
|
CSET programmable_empty_type_rdch=Empty
|
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
|
CSET programmable_empty_type_wach=Empty
|
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
|
CSET programmable_empty_type_wdch=Empty
|
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
|
CSET programmable_empty_type_wrch=Empty
|
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
|
CSET programmable_full_type=No_Programmable_Full_Threshold
|
CSET programmable_full_type=No_Programmable_Full_Threshold
|
CSET programmable_full_type_axis=Full
|
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
|
CSET programmable_full_type_rach=Full
|
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
|
CSET programmable_full_type_rdch=Full
|
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
|
CSET programmable_full_type_wach=Full
|
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
|
CSET programmable_full_type_wdch=Full
|
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
|
CSET programmable_full_type_wrch=Full
|
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
|
CSET rach_type=FIFO
|
CSET rach_type=FIFO
|
CSET rdch_type=FIFO
|
CSET rdch_type=FIFO
|
CSET read_clock_frequency=1
|
CSET read_clock_frequency=1
|
CSET read_data_count=false
|
CSET read_data_count=false
|
CSET read_data_count_width=9
|
CSET read_data_count_width=9
|
Line 182... |
Line 176... |
CSET register_slice_mode_wdch=Fully_Registered
|
CSET register_slice_mode_wdch=Fully_Registered
|
CSET register_slice_mode_wrch=Fully_Registered
|
CSET register_slice_mode_wrch=Fully_Registered
|
CSET reset_pin=true
|
CSET reset_pin=true
|
CSET reset_type=Asynchronous_Reset
|
CSET reset_type=Asynchronous_Reset
|
CSET ruser_width=1
|
CSET ruser_width=1
|
|
CSET synchronization_stages=2
|
|
CSET synchronization_stages_axi=2
|
CSET tdata_width=64
|
CSET tdata_width=64
|
CSET tdest_width=4
|
CSET tdest_width=4
|
CSET tid_width=8
|
CSET tid_width=8
|
CSET tkeep_width=4
|
CSET tkeep_width=4
|
CSET tstrb_width=4
|
CSET tstrb_width=4
|
Line 209... |
Line 205... |
CSET write_data_count=false
|
CSET write_data_count=false
|
CSET write_data_count_width=9
|
CSET write_data_count_width=9
|
CSET wuser_width=1
|
CSET wuser_width=1
|
# END Parameters
|
# END Parameters
|
# BEGIN Extra information
|
# BEGIN Extra information
|
MISC pkg_timestamp=2011-03-14T07:12:32.000Z
|
MISC pkg_timestamp=2012-11-19T12:39:56Z
|
# END Extra information
|
# END Extra information
|
GENERATE
|
GENERATE
|
# CRC: c15403dd
|
# CRC: e84e4d4d
|
# CRC: e84e4d4d
|
# CRC: e84e4d4d
|