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use work.core64_type_pkg.all;
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use work.core64_type_pkg.all;
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use work.pcie_core64_m1_pkg.all;
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use work.pcie_core64_m1_pkg.all;
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use work.core64_pb_wishbone_pkg.all;
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use work.core64_pb_wishbone_pkg.all;
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use work.block_pe_main_pkg.all;
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use work.block_pe_main_pkg.all;
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library unisim;
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use unisim.vcomponents.all;
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entity pcie_core64_wishbone_m8 is
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entity pcie_core64_wishbone_m8 is
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generic
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generic
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(
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(
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Device_ID : in std_logic_vector( 15 downto 0 ):=x"0000"; -- идентификатор модуля
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Device_ID : in std_logic_vector( 15 downto 0 ):=x"0000"; -- идентификатор модуля
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Revision : in std_logic_vector( 15 downto 0 ):=x"0000"; -- версия модуля
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Revision : in std_logic_vector( 15 downto 0 ):=x"0000"; -- версия модуля
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signal reset : std_logic;
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signal reset : std_logic;
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signal dcm_rst_out : std_logic;
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signal dcm_rst_out : std_logic;
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signal reset_p : std_logic;
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signal reset_p : std_logic;
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signal reset_p_z1 : std_logic;
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signal reset_p_z1 : std_logic;
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signal reset_p_z2 : std_logic;
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signal reset_p_z2 : std_logic;
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signal clk125x : std_logic:='0';
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signal clk125 : std_logic;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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begin
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begin
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Instantiate CORE64_M6 module with PB BUS:
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-- Instantiate CORE64_M6 module with PB BUS:
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clk_out => clk, -- S6 PCIE x1 module clock output
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clk_out => clk, -- S6 PCIE x1 module clock output
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reset_out => reset, --
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reset_out => reset, --
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dcm_rstp => dcm_rst_out, -- S6 PCIE x1 module INV trn_reset_n_c
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dcm_rstp => dcm_rst_out, -- S6 PCIE x1 module INV trn_reset_n_c
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---- BAR1 (PB bus) ----
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---- BAR1 (PB bus) ----
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aclk => clk, -- !!! same clock as clk_out
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aclk => clk125,
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aclk_lock => '1', --
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aclk_lock => '1', --
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pb_master => pb_master, --
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pb_master => pb_master, --
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pb_slave => pb_slave, --
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pb_slave => pb_slave, --
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---- BAR0 (to PE_MAIN) - блоки управления ----
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---- BAR0 (to PE_MAIN) - блоки управления ----
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bp_reg_rd => bp_reg_rd,
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bp_reg_rd => bp_reg_rd,
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bp_irq => bp_irq
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bp_irq => bp_irq
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);
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);
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clk125x <= not clk125x after 0.5 ns when rising_edge( clk );
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xclk125: bufg port map( clk125, clk125x );
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reset_p <= (not reset) or (not brd_mode(3));
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reset_p <= (not reset) or (not brd_mode(3));
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reset_p_z1 <= reset_p after 1 ns when rising_edge( clk );
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reset_p_z1 <= reset_p after 1 ns when rising_edge( clk125 );
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reset_p_z2 <= reset_p_z1 after 1 ns when rising_edge( clk );
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reset_p_z2 <= reset_p_z1 after 1 ns when rising_edge( clk125 );
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-- Deal with CORE BP Input data:
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-- Deal with CORE BP Input data:
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bp_data <= bp0_data when bp_sel="00" else (others=>'0');
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bp_data <= bp0_data when bp_sel="00" else (others=>'0');
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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--
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--
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PW_WB : core64_pb_wishbone
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PW_WB : core64_pb_wishbone
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port map
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port map
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(
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(
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reset => reset_p_z2, --! 1 - сброс
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reset => reset_p_z2, --! 1 - сброс
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clk => clk, --! тактовая частота локальной шины
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clk => clk125, --! тактовая частота локальной шины
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---- BAR1 ----
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---- BAR1 ----
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pb_master => pb_master, --! запрос
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pb_master => pb_master, --! запрос
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pb_slave => pb_slave, --! ответ
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pb_slave => pb_slave, --! ответ
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);
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);
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Module Output route:
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-- Module Output route:
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--
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--
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o_wb_clk <= clk; -- route from PW_WB wrk clock
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o_wb_clk <= clk125; -- route from PW_WB wrk clock
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--
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--
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pr_o_wb_rst: process( reset_p, clk ) begin
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pr_o_wb_rst: process( reset_p, clk125 ) begin
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if( reset_p='1' ) then
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if( reset_p='1' ) then
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o_wb_rst <= '1' after 1 ns;
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o_wb_rst <= '1' after 1 ns;
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elsif( rising_edge( clk ) ) then
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elsif( rising_edge( clk125 ) ) then
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o_wb_rst <= reset_p_z2 after 1 ns;
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o_wb_rst <= reset_p_z2 after 1 ns;
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end if;
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end if;
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end process;
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end process;
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