| Line 58... |
Line 58... |
end package;
|
end package;
|
|
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
|
use ieee.std_logic_arith.all;
|
|
use ieee.std_logic_unsigned.all;
|
|
|
library unisim;
|
library unisim;
|
use unisim.vcomponents.all;
|
use unisim.vcomponents.all;
|
|
|
use work.core64_type_pkg.all;
|
use work.core64_type_pkg.all;
|
| Line 130... |
Line 132... |
signal reg_data_we_clr_z1 : std_logic;
|
signal reg_data_we_clr_z1 : std_logic;
|
signal reg_data_we_clr_z2 : std_logic;
|
signal reg_data_we_clr_z2 : std_logic;
|
|
|
signal reg_complete : std_logic;
|
signal reg_complete : std_logic;
|
|
|
|
signal timeout_cnt : std_logic_vector( 12 downto 0 );
|
|
signal slave_timeout : std_logic;
|
|
|
attribute tig : string;
|
attribute tig : string;
|
attribute tig of master_adr : signal is "";
|
attribute tig of master_adr : signal is "";
|
attribute tig of dmar : signal is "";
|
attribute tig of dmar : signal is "";
|
attribute tig of rstp : signal is "";
|
attribute tig of rstp : signal is "";
|
|
|
| Line 184... |
Line 189... |
reg_data_we_set <= '0' after 1 ns;
|
reg_data_we_set <= '0' after 1 ns;
|
fifo_allow_wr <= '0' after 1 ns;
|
fifo_allow_wr <= '0' after 1 ns;
|
reg_stb1 <= '0' after 1 ns;
|
reg_stb1 <= '0' after 1 ns;
|
fifo_data_en <= '0' after 1 ns;
|
fifo_data_en <= '0' after 1 ns;
|
ext_fifo_disp_back.complete <= '0' after 1 ns;
|
ext_fifo_disp_back.complete <= '0' after 1 ns;
|
|
timeout_cnt <= (others=>'0') after 1 ns;
|
|
|
if( reg_req_wr_z='1' or reg_req_rd_z='1' ) then
|
if( reg_req_wr_z='1' or reg_req_rd_z='1' ) then
|
stp <= sr1 after 1 ns;
|
stp <= sr1 after 1 ns;
|
elsif( ext_fifo_disp.request_wr='1' or ext_fifo_disp.request_rd='1' ) then
|
elsif( ext_fifo_disp.request_wr='1' or ext_fifo_disp.request_rd='1' ) then
|
stp <= sf1 after 1 ns;
|
stp <= sf1 after 1 ns;
|
| Line 213... |
Line 219... |
-- stp <= sr4 after 1 ns;
|
-- stp <= sr4 after 1 ns;
|
-- else
|
-- else
|
-- stp <= sr5 after 1 ns;
|
-- stp <= sr5 after 1 ns;
|
-- end if;
|
-- end if;
|
-- end if;
|
-- end if;
|
|
timeout_cnt <= timeout_cnt + 1 after 1 ns;
|
reg_data_we_set <= pb_slave.stb1 after 1 ns;
|
reg_data_we_set <= pb_slave.stb1 after 1 ns;
|
if( pb_slave.complete='1' ) then
|
if( pb_slave.complete='1' or slave_timeout='1') then
|
stp <= sr5 after 1 ns;
|
stp <= sr5 after 1 ns;
|
end if;
|
end if;
|
|
|
|
|
-- when sr4 => ---- Îæèäàíèå äàííûõ ----
|
-- when sr4 => ---- Îæèäàíèå äàííûõ ----
|
| Line 247... |
Line 254... |
|
|
when sf2 =>
|
when sf2 =>
|
master_stb0 <= '0' after 1 ns; -- ñòðîá êîìàíäû
|
master_stb0 <= '0' after 1 ns; -- ñòðîá êîìàíäû
|
fifo_allow_wr <= ext_fifo_disp.request_wr and pb_slave.ready after 1 ns;
|
fifo_allow_wr <= ext_fifo_disp.request_wr and pb_slave.ready after 1 ns;
|
fifo_data_en <= '1' after 1 ns;
|
fifo_data_en <= '1' after 1 ns;
|
if( pb_slave.complete='1' ) then
|
timeout_cnt <= timeout_cnt + 1 after 1 ns;
|
|
if( pb_slave.complete='1' or slave_timeout='1' ) then
|
ext_fifo_disp_back.complete <= '1' after 1 ns;
|
ext_fifo_disp_back.complete <= '1' after 1 ns;
|
stp <= sf3 after 1 ns;
|
stp <= sf3 after 1 ns;
|
end if;
|
end if;
|
|
|
when sf3 =>
|
when sf3 =>
|
| Line 269... |
Line 277... |
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
slave_timeout <= timeout_cnt(12) after 1 ns when rising_edge( clk );
|
|
|
ext_fifo_disp_back.allow_wr <= fifo_allow_wr;
|
ext_fifo_disp_back.allow_wr <= fifo_allow_wr;
|
|
|
pb_slave_stb1_z <= pb_slave.stb1 after 1 ns when rising_edge( aclk );
|
pb_slave_stb1_z <= pb_slave.stb1 after 1 ns when rising_edge( aclk );
|
ex_fifo_stb1_z <= ext_fifo_disp.data_we after 1 ns when rising_edge( aclk );
|
ex_fifo_stb1_z <= ext_fifo_disp.data_we after 1 ns when rising_edge( aclk );
|
|
|
