Line 58... |
Line 58... |
end package;
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end package;
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library unisim;
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library unisim;
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use unisim.vcomponents.all;
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use unisim.vcomponents.all;
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use work.core64_type_pkg.all;
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use work.core64_type_pkg.all;
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Line 130... |
Line 132... |
signal reg_data_we_clr_z1 : std_logic;
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signal reg_data_we_clr_z1 : std_logic;
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signal reg_data_we_clr_z2 : std_logic;
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signal reg_data_we_clr_z2 : std_logic;
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signal reg_complete : std_logic;
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signal reg_complete : std_logic;
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signal timeout_cnt : std_logic_vector( 12 downto 0 );
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signal slave_timeout : std_logic;
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attribute tig : string;
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attribute tig : string;
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attribute tig of master_adr : signal is "";
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attribute tig of master_adr : signal is "";
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attribute tig of dmar : signal is "";
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attribute tig of dmar : signal is "";
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attribute tig of rstp : signal is "";
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attribute tig of rstp : signal is "";
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Line 184... |
Line 189... |
reg_data_we_set <= '0' after 1 ns;
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reg_data_we_set <= '0' after 1 ns;
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fifo_allow_wr <= '0' after 1 ns;
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fifo_allow_wr <= '0' after 1 ns;
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reg_stb1 <= '0' after 1 ns;
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reg_stb1 <= '0' after 1 ns;
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fifo_data_en <= '0' after 1 ns;
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fifo_data_en <= '0' after 1 ns;
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ext_fifo_disp_back.complete <= '0' after 1 ns;
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ext_fifo_disp_back.complete <= '0' after 1 ns;
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timeout_cnt <= (others=>'0') after 1 ns;
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if( reg_req_wr_z='1' or reg_req_rd_z='1' ) then
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if( reg_req_wr_z='1' or reg_req_rd_z='1' ) then
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stp <= sr1 after 1 ns;
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stp <= sr1 after 1 ns;
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elsif( ext_fifo_disp.request_wr='1' or ext_fifo_disp.request_rd='1' ) then
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elsif( ext_fifo_disp.request_wr='1' or ext_fifo_disp.request_rd='1' ) then
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stp <= sf1 after 1 ns;
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stp <= sf1 after 1 ns;
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Line 213... |
Line 219... |
-- stp <= sr4 after 1 ns;
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-- stp <= sr4 after 1 ns;
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-- else
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-- else
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-- stp <= sr5 after 1 ns;
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-- stp <= sr5 after 1 ns;
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-- end if;
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-- end if;
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-- end if;
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-- end if;
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timeout_cnt <= timeout_cnt + 1 after 1 ns;
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reg_data_we_set <= pb_slave.stb1 after 1 ns;
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reg_data_we_set <= pb_slave.stb1 after 1 ns;
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if( pb_slave.complete='1' ) then
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if( pb_slave.complete='1' or slave_timeout='1') then
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stp <= sr5 after 1 ns;
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stp <= sr5 after 1 ns;
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end if;
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end if;
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-- when sr4 => ---- Îæèäàíèå äàííûõ ----
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-- when sr4 => ---- Îæèäàíèå äàííûõ ----
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Line 247... |
Line 254... |
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when sf2 =>
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when sf2 =>
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master_stb0 <= '0' after 1 ns; -- ñòðîá êîìàíäû
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master_stb0 <= '0' after 1 ns; -- ñòðîá êîìàíäû
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fifo_allow_wr <= ext_fifo_disp.request_wr and pb_slave.ready after 1 ns;
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fifo_allow_wr <= ext_fifo_disp.request_wr and pb_slave.ready after 1 ns;
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fifo_data_en <= '1' after 1 ns;
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fifo_data_en <= '1' after 1 ns;
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if( pb_slave.complete='1' ) then
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timeout_cnt <= timeout_cnt + 1 after 1 ns;
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if( pb_slave.complete='1' or slave_timeout='1' ) then
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ext_fifo_disp_back.complete <= '1' after 1 ns;
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ext_fifo_disp_back.complete <= '1' after 1 ns;
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stp <= sf3 after 1 ns;
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stp <= sf3 after 1 ns;
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end if;
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end if;
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when sf3 =>
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when sf3 =>
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Line 269... |
Line 277... |
end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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slave_timeout <= timeout_cnt(12) after 1 ns when rising_edge( clk );
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ext_fifo_disp_back.allow_wr <= fifo_allow_wr;
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ext_fifo_disp_back.allow_wr <= fifo_allow_wr;
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pb_slave_stb1_z <= pb_slave.stb1 after 1 ns when rising_edge( aclk );
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pb_slave_stb1_z <= pb_slave.stb1 after 1 ns when rising_edge( aclk );
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ex_fifo_stb1_z <= ext_fifo_disp.data_we after 1 ns when rising_edge( aclk );
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ex_fifo_stb1_z <= ext_fifo_disp.data_we after 1 ns when rising_edge( aclk );
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