URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [pcie_ctrl/] [core64_tx_engine_m4.vhd] - Diff between revs 2 and 11

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Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [pcie_ctrl/] [core64_tx_engine_m4.vhd] - Diff between revs 2 and 11

Rev 2	Rev 11
Line 15...	Line 15...
`-------------------------------------------------------------------------------`	`-------------------------------------------------------------------------------`
`--`	`--`
`-- Version 1.1 19.06.2012`	`-- Version 1.1 19.06.2012`
`-- �� cpl_byte_count`	`-- �� cpl_byte_count`
`--`	`--`
	`-- 12.04.2013`
	`-- Fixed cpl_byte_count`
	`--`
`-------------------------------------------------------------------------------`	`-------------------------------------------------------------------------------`

`library ieee;`	`library ieee;`
`use ieee.std_logic_1164.all;`	`use ieee.std_logic_1164.all;`

Line 456...	Line 459...

`tlp_dw0 <= "0" & rx_tx_engine.request_reg_rd & "0010100" & rx_tx_engine.request_tc & "0000" & rx_tx_engine.request_attr & "0000" & "0000000" & rx_tx_engine.request_reg_rd;`	`tlp_dw0 <= "0" & rx_tx_engine.request_reg_rd & "0010100" & rx_tx_engine.request_tc & "0000" & rx_tx_engine.request_attr & "0000" & "0000000" & rx_tx_engine.request_reg_rd;`
`tlp_dw1 <= completer_id & cpl_status & '0' & cpl_byte_count;`	`tlp_dw1 <= completer_id & cpl_status & '0' & cpl_byte_count;`
`tlp_dw2 <= rx_tx_engine.request_id & rx_tx_engine.request_tag & '0' & rx_tx_engine.lower_adr & "00";`	`tlp_dw2 <= rx_tx_engine.request_id & rx_tx_engine.request_tag & '0' & rx_tx_engine.lower_adr & "00";`

`cpl_byte_count <= "0000" & "0000" & "0" & rx_tx_engine.request_reg_rd & "00";`	`--cpl_byte_count <= "0000" & "0000" & "0" & rx_tx_engine.request_reg_rd & "00";`
`cpl_byte_count <= "0000" & "0000" & "0" & rx_tx_engine.byte_count;`	`cpl_byte_count <= "0000" & "0000" & "0" & rx_tx_engine.byte_count;`

`reg_data <= reg_access_back.data after 1 ns when rising_edge( clk ) and reg_access_back.data_we='1';`	`reg_data <= reg_access_back.data after 1 ns when rising_edge( clk ) and reg_access_back.data_we='1';`
`tlp_dw3( 7 downto 0 ) <= reg_data( 31 downto 24 );`	`tlp_dw3( 7 downto 0 ) <= reg_data( 31 downto 24 );`
`tlp_dw3( 15 downto 8 ) <= reg_data( 23 downto 16 );`	`tlp_dw3( 15 downto 8 ) <= reg_data( 23 downto 16 );`