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-- PART OF THIS FILE AT ALL TIMES.
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-- PART OF THIS FILE AT ALL TIMES.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Project : Series-7 Integrated Block for PCI Express
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-- Project : Series-7 Integrated Block for PCI Express
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-- File : cl_a7pcie_x4.vhd
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-- File : cl_a7pcie_x4.vhd
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-- Version : 1.9
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-- Version : 1.10
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--
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--
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-- Description: Solution wrapper for Virtex7 Hard Block for PCI Express
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-- Description: Solution wrapper for Virtex7 Hard Block for PCI Express
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--
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--
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--
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--
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--
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--
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| Line 63... |
Line 63... |
use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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|
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entity cl_a7pcie_x4 is
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entity cl_a7pcie_x4 is
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generic (
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generic (
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CFG_VEND_ID : std_logic_vector := X"4953";
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CFG_VEND_ID : std_logic_vector := X"10EE";
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CFG_DEV_ID : std_logic_vector := X"5507";
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CFG_DEV_ID : std_logic_vector := X"7024";
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CFG_REV_ID : std_logic_vector := X"00";
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CFG_REV_ID : std_logic_vector := X"00";
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CFG_SUBSYS_VEND_ID : std_logic_vector := X"10EE";
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CFG_SUBSYS_VEND_ID : std_logic_vector := X"10EE";
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CFG_SUBSYS_ID : std_logic_vector := X"0701";
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CFG_SUBSYS_ID : std_logic_vector := X"0007";
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ALLOW_X8_GEN2 : string := "FALSE";
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ALLOW_X8_GEN2 : string := "FALSE";
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PIPE_PIPELINE_STAGES : integer := 1;
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PIPE_PIPELINE_STAGES : integer := 1;
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AER_BASE_PTR : bit_vector := X"000";
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AER_BASE_PTR : bit_vector := X"000";
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AER_CAP_ECRC_CHECK_CAPABLE : string := "FALSE";
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AER_CAP_ECRC_CHECK_CAPABLE : string := "FALSE";
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AER_CAP_ECRC_GEN_CAPABLE : string := "FALSE";
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AER_CAP_MULTIHEADER : string := "FALSE";
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AER_CAP_MULTIHEADER : string := "FALSE";
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AER_CAP_NEXTPTR : bit_vector := X"000";
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AER_CAP_NEXTPTR : bit_vector := X"000";
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AER_CAP_OPTIONAL_ERR_SUPPORT : bit_vector := X"000000";
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AER_CAP_OPTIONAL_ERR_SUPPORT : bit_vector := X"000000";
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AER_CAP_ON : string := "FALSE";
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AER_CAP_ON : string := "FALSE";
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AER_CAP_PERMIT_ROOTERR_UPDATE : string := "FALSE";
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AER_CAP_PERMIT_ROOTERR_UPDATE : string := "FALSE";
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| Line 87... |
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BAR4 : bit_vector := X"00000000";
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BAR4 : bit_vector := X"00000000";
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BAR5 : bit_vector := X"00000000";
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BAR5 : bit_vector := X"00000000";
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C_DATA_WIDTH : integer := 64;
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C_DATA_WIDTH : integer := 64;
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CARDBUS_CIS_POINTER : bit_vector := X"00000000";
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CARDBUS_CIS_POINTER : bit_vector := X"00000000";
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CLASS_CODE : bit_vector := X"FFFFFF";
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CLASS_CODE : bit_vector := X"058000";
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CMD_INTX_IMPLEMENTED : string := "TRUE";
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CMD_INTX_IMPLEMENTED : string := "TRUE";
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CPL_TIMEOUT_DISABLE_SUPPORTED : string := "FALSE";
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CPL_TIMEOUT_DISABLE_SUPPORTED : string := "FALSE";
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CPL_TIMEOUT_RANGES_SUPPORTED : bit_vector := X"2";
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CPL_TIMEOUT_RANGES_SUPPORTED : bit_vector := X"2";
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DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 0;
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DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 0;
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MSIX_CAP_TABLE_SIZE : bit_vector := X"0";
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MSIX_CAP_TABLE_SIZE : bit_vector := X"0";
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|
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PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := X"0";
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PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := X"0";
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PCIE_CAP_NEXTPTR : bit_vector := X"00";
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PCIE_CAP_NEXTPTR : bit_vector := X"00";
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PM_CAP_DSI : string := "TRUE";
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PM_CAP_DSI : string := "FALSE";
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PM_CAP_D1SUPPORT : string := "FALSE";
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PM_CAP_D1SUPPORT : string := "FALSE";
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PM_CAP_D2SUPPORT : string := "FALSE";
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PM_CAP_D2SUPPORT : string := "FALSE";
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PM_CAP_NEXTPTR : bit_vector := X"60";
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PM_CAP_NEXTPTR : bit_vector := X"60";
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PM_CAP_PMESUPPORT : bit_vector := X"0F";
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PM_CAP_PMESUPPORT : bit_vector := X"0F";
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PM_CSR_NOSOFTRST : string := "TRUE";
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PM_CSR_NOSOFTRST : string := "TRUE";
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PCIE_CAP_SLOT_IMPLEMENTED : string := "FALSE";
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PCIE_CAP_SLOT_IMPLEMENTED : string := "FALSE";
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PCIE_REVISION : integer := 2;
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PCIE_REVISION : integer := 2;
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PL_AUTO_CONFIG : integer := 0;
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PL_AUTO_CONFIG : integer := 0;
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PL_FAST_TRAIN : string := "FALSE";
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PL_FAST_TRAIN : string := "FALSE";
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PCIE_EXT_CLK : string := "TRUE";
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PCIE_EXT_CLK : string := "TRUE";
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PM_BASE_PTR : bit_vector := X"40";
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PM_BASE_PTR : bit_vector := X"40";
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PM_CAP_AUXCURRENT : integer := 0;
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PM_CAP_AUXCURRENT : integer := 0;
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PM_CAP_ID : bit_vector := X"01";
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PM_CAP_ID : bit_vector := X"01";
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| Line 396... |
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DEV_CAP2_MAX_ENDEND_TLP_PREFIXES : bit_vector := X"0";
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DEV_CAP2_MAX_ENDEND_TLP_PREFIXES : bit_vector := X"0";
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DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING : string := "FALSE";
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DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING : string := "FALSE";
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LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE : string := "FALSE";
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LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE : string := "FALSE";
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AER_CAP_ECRC_GEN_CAPABLE : string := "FALSE";
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AER_CAP_ID : bit_vector := X"0001";
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AER_CAP_ID : bit_vector := X"0001";
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AER_CAP_VERSION : bit_vector := X"1";
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AER_CAP_VERSION : bit_vector := X"1";
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RBAR_CAP_ID : bit_vector := X"0015";
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RBAR_CAP_ID : bit_vector := X"0015";
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RBAR_CAP_NEXTPTR : bit_vector := X"000";
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RBAR_CAP_NEXTPTR : bit_vector := X"000";
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| Line 655... |
Line 656... |
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architecture pcie_7x of cl_a7pcie_x4 is
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architecture pcie_7x of cl_a7pcie_x4 is
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|
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attribute CORE_GENERATION_INFO : string;
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attribute CORE_GENERATION_INFO : string;
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attribute CORE_GENERATION_INFO of pcie_7x : ARCHITECTURE is
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attribute CORE_GENERATION_INFO of pcie_7x : ARCHITECTURE is
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"cl_a7pcie_x4,pcie_7x_v1_9,{LINK_CAP_MAX_LINK_SPEED=2,LINK_CAP_MAX_LINK_WIDTH=04,PCIE_CAP_DEVICE_PORT_TYPE=0000,DEV_CAP_MAX_PAYLOAD_SUPPORTED=1,USER_CLK_FREQ=3,REF_CLK_FREQ=0,MSI_CAP_ON=FALSE,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,MSIX_CAP_ON=FALSE,TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=28,VC0_RX_RAM_LIMIT=3FF,VC0_TOTAL_CREDITS_PH=4,VC0_TOTAL_CREDITS_PD=32,VC0_TOTAL_CREDITS_NPH=4,VC0_TOTAL_CREDITS_NPD=8,VC0_TOTAL_CREDITS_CH=72,VC0_TOTAL_CREDITS_CD=370,VC0_CPL_INFINITE=TRUE,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,LINK_STATUS_SLOT_CLOCK_CONFIG=TRUE,ENABLE_RX_TD_ECRC_TRIM=TRUE,DISABLE_LANE_REVERSAL=TRUE,DISABLE_SCRAMBLING=FALSE,DSN_CAP_ON=TRUE,REVISION_ID=00,VC_CAP_ON=FALSE}";
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"cl_a7pcie_x4,pcie_7x_v1_10,{LINK_CAP_MAX_LINK_SPEED=2,LINK_CAP_MAX_LINK_WIDTH=04,PCIE_CAP_DEVICE_PORT_TYPE=0000,DEV_CAP_MAX_PAYLOAD_SUPPORTED=1,USER_CLK_FREQ=3,REF_CLK_FREQ=0,MSI_CAP_ON=FALSE,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,MSIX_CAP_ON=FALSE,TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=28,VC0_RX_RAM_LIMIT=3FF,VC0_TOTAL_CREDITS_PH=4,VC0_TOTAL_CREDITS_PD=32,VC0_TOTAL_CREDITS_NPH=4,VC0_TOTAL_CREDITS_NPD=8,VC0_TOTAL_CREDITS_CH=72,VC0_TOTAL_CREDITS_CD=370,VC0_CPL_INFINITE=TRUE,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,LINK_STATUS_SLOT_CLOCK_CONFIG=TRUE,ENABLE_RX_TD_ECRC_TRIM=TRUE,DISABLE_LANE_REVERSAL=TRUE,DISABLE_SCRAMBLING=FALSE,DSN_CAP_ON=TRUE,REVISION_ID=00,VC_CAP_ON=FALSE}";
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component cl_a7pcie_x4_pcie_top is
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component cl_a7pcie_x4_pcie_top is
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generic (
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generic (
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C_DATA_WIDTH : INTEGER range 32 to 128 := 64;
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C_DATA_WIDTH : INTEGER range 32 to 128 := 64;
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C_REM_WIDTH : INTEGER range 0 to 128 := 1;
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C_REM_WIDTH : INTEGER range 0 to 128 := 1;
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PIPE_PIPELINE_STAGES : INTEGER range 0 to 2 := 0; -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
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PIPE_PIPELINE_STAGES : INTEGER range 0 to 2 := 0; -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
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