| Line 47... |
Line 47... |
// PART OF THIS FILE AT ALL TIMES.
|
// PART OF THIS FILE AT ALL TIMES.
|
//
|
//
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Project : Series-7 Integrated Block for PCI Express
|
// Project : Series-7 Integrated Block for PCI Express
|
// File : cl_a7pcie_x4_gtp_pipe_drp.v
|
// File : cl_a7pcie_x4_gtp_pipe_drp.v
|
// Version : 1.9
|
// Version : 1.10
|
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
// Filename : gtp_pipe_drp.v
|
// Filename : gtp_pipe_drp.v
|
// Description : GTP PIPE DRP Module for 7 Series Transceiver
|
// Description : GTP PIPE DRP Module for 7 Series Transceiver
|
// Version : 19.0
|
// Version : 19.0
|
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
| Line 90... |
Line 90... |
output [ 2:0] DRP_FSM
|
output [ 2:0] DRP_FSM
|
|
|
);
|
);
|
|
|
//---------- Input Registers ---------------------------
|
//---------- Input Registers ---------------------------
|
reg x16_reg1;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg1;
|
reg start_reg1;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1;
|
reg [15:0] do_reg1;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1;
|
reg rdy_reg1;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1;
|
|
|
reg x16_reg2;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg2;
|
reg start_reg2;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2;
|
reg [15:0] do_reg2;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2;
|
reg rdy_reg2;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2;
|
|
|
//---------- Internal Signals --------------------------
|
//---------- Internal Signals --------------------------
|
reg [ 1:0] load_cnt = 2'd0;
|
reg [ 1:0] load_cnt = 2'd0;
|
reg [ 4:0] index = 5'd0;
|
reg [ 4:0] index = 5'd0;
|
reg [ 8:0] addr_reg = 9'd0;
|
reg [ 8:0] addr_reg = 9'd0;
|
reg [15:0] di_reg = 16'd0;
|
reg [15:0] di_reg = 16'd0;
|
|
|
//---------- Output Registers --------------------------
|
//---------- Output Registers --------------------------
|
reg done = 1'd0;
|
reg done = 1'd0;
|
reg [ 2:0] fsm = 1;
|
reg [ 2:0] fsm = 0;
|
|
|
//---------- DRP Address -------------------------------
|
//---------- DRP Address -------------------------------
|
localparam ADDR_RX_DATAWIDTH = 9'h011;
|
localparam ADDR_RX_DATAWIDTH = 9'h011;
|
|
|
//---------- DRP Mask ----------------------------------
|
//---------- DRP Mask ----------------------------------
|
