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// PART OF THIS FILE AT ALL TIMES.
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// PART OF THIS FILE AT ALL TIMES.
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_pipe_clock.v
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// File : cl_a7pcie_x4_pipe_clock.v
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// Version : 1.9
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// Version : 1.10
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Filename : pipe_clock.v
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// Filename : pipe_clock.v
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// Description : PIPE Clock Module for 7 Series Transceiver
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// Description : PIPE Clock Module for 7 Series Transceiver
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// Version : 15.3
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// Version : 15.3
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//---------- Select Reference Clock --------------------
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//---------- Select Reference Clock --------------------
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localparam REFCLK_SEL = ((PCIE_TXBUF_EN == "TRUE") && (PCIE_LINK_SPEED != 3)) ? 1'd1 : 1'd0;
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localparam REFCLK_SEL = ((PCIE_TXBUF_EN == "TRUE") && (PCIE_LINK_SPEED != 3)) ? 1'd1 : 1'd0;
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//---------- Input Registers ---------------------------
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//---------- Input Registers ---------------------------
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reg [PCIE_LANE-1:0] pclk_sel_reg1 = {PCIE_LANE{1'd0}};
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_reg1 = {PCIE_LANE{1'd0}};
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reg gen3_reg1 = 1'd0;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1 = 1'd0;
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reg [PCIE_LANE-1:0] pclk_sel_reg2 = {PCIE_LANE{1'd0}};
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_reg2 = {PCIE_LANE{1'd0}};
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reg gen3_reg2 = 1'd0;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2 = 1'd0;
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//---------- Internal Signals --------------------------
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//---------- Internal Signals --------------------------
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wire refclk;
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wire refclk;
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wire mmcm_fb;
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wire mmcm_fb;
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wire clk_125mhz;
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wire clk_125mhz;
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