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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source_artix7/] [cl_a7pcie_x4_pipe_sync.v] - Diff between revs 46 and 48

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Line 47... Line 47... 
// PART OF THIS FILE AT ALL TIMES.
 
// PART OF THIS FILE AT ALL TIMES.
 
//
 
//
 
//-----------------------------------------------------------------------------
 
//-----------------------------------------------------------------------------
 
// Project    : Series-7 Integrated Block for PCI Express
 
// Project    : Series-7 Integrated Block for PCI Express
 
// File       : cl_a7pcie_x4_pipe_sync.v
 
// File       : cl_a7pcie_x4_pipe_sync.v
 
// Version    : 1.9
 
// Version    : 1.10
 
//------------------------------------------------------------------------------
 
//------------------------------------------------------------------------------
 
//  Filename     :  pipe_sync.v
 
//  Filename     :  pipe_sync.v
 
//  Description  :  PIPE Sync Module for 7 Series Transceiver
 
//  Description  :  PIPE Sync Module for 7 Series Transceiver
 
//  Version      :  20.1
 
//  Version      :  20.1
 
//------------------------------------------------------------------------------
 
//------------------------------------------------------------------------------
Line 131... Line 131... 
    output    [ 6:0]    SYNC_FSM_RX
 
    output    [ 6:0]    SYNC_FSM_RX
 
 
 
 
 
);
 
);
 
 
 
 
 
    //---------- Input Register ----------------------------
 
    //---------- Input Register ----------------------------
 
    reg                 gen3_reg1;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 gen3_reg1;
 
    reg                 rate_idle_reg1;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rate_idle_reg1;
 
    reg                             mmcm_lock_reg1;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 mmcm_lock_reg1;
 
    reg                 rxelecidle_reg1;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxelecidle_reg1;
 
    reg                 rxcdrlock_reg1;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxcdrlock_reg1;
 
 
 
 
 
    reg                 gen3_reg2;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 gen3_reg2;
 
    reg                 rate_idle_reg2;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rate_idle_reg2;
 
    reg                                   mmcm_lock_reg2;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 mmcm_lock_reg2;
 
    reg                 rxelecidle_reg2;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxelecidle_reg2;
 
    reg                 rxcdrlock_reg2;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxcdrlock_reg2;
 
 
 
 
 
    reg                                         txsync_start_reg1;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txsync_start_reg1;
 
    reg                 txphinitdone_reg1;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txphinitdone_reg1;
 
    reg                 txdlysresetdone_reg1;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txdlysresetdone_reg1;
 
    reg                 txphaligndone_reg1;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txphaligndone_reg1;
 
    reg                 txsyncdone_reg1;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txsyncdone_reg1;
 
 
 
 
 
    reg                 txsync_start_reg2;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txsync_start_reg2;
 
    reg                 txphinitdone_reg2;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txphinitdone_reg2;
 
    reg                 txdlysresetdone_reg2;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txdlysresetdone_reg2;
 
    reg                 txphaligndone_reg2;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txphaligndone_reg2;
 
    reg                 txsyncdone_reg2;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txsyncdone_reg2;
 
 
 
 
 
    reg                                         rxsync_start_reg1;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txsync_start_reg3;
 
    reg                 rxdlysresetdone_reg1;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txphinitdone_reg3;
 
    reg                 rxphaligndone_m_reg1;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txdlysresetdone_reg3;
 
    reg                 rxphaligndone_s_reg1;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txphaligndone_reg3;
 
    reg                 rxsync_donem_reg1;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txsyncdone_reg3;
 
    reg                 rxsyncdone_reg1;
 
 
 
 
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxsync_start_reg1;
 
    reg                                         rxsync_start_reg2;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxdlysresetdone_reg1;
 
    reg                 rxdlysresetdone_reg2;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxphaligndone_m_reg1;
 
    reg                 rxphaligndone_m_reg2;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxphaligndone_s_reg1;
 
    reg                 rxphaligndone_s_reg2;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxsync_donem_reg1;
 
    reg                 rxsync_donem_reg2;
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxsyncdone_reg1;
 
    reg                 rxsyncdone_reg2;
 
 
 
 
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxsync_start_reg2;
 
 
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxdlysresetdone_reg2;
 
 
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxphaligndone_m_reg2;
 
 
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxphaligndone_s_reg2;
 
 
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxsync_donem_reg2;
 
 
 
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxsyncdone_reg2;
 
 
 
 
 
    //---------- Output Register ---------------------------          
    //---------- Output Register ---------------------------          
    reg                 txdlyen     = 1'd0;
 
    reg                 txdlyen     = 1'd0;
 
    reg                 txsync_done = 1'd0;
 
    reg                 txsync_done = 1'd0;
 
    reg         [ 5:0]  fsm_tx      = 6'd0;
 
    reg         [ 5:0]  fsm_tx      = 6'd0;
Line 240... Line 246... 
        rxdlysresetdone_reg2 <= 1'd0;
 
        rxdlysresetdone_reg2 <= 1'd0;
 
        rxphaligndone_m_reg2 <= 1'd0;
 
        rxphaligndone_m_reg2 <= 1'd0;
 
        rxphaligndone_s_reg2 <= 1'd0;
 
        rxphaligndone_s_reg2 <= 1'd0;
 
        rxsync_donem_reg2    <= 1'd0;
 
        rxsync_donem_reg2    <= 1'd0;
 
        rxsyncdone_reg2      <= 1'd0;
 
        rxsyncdone_reg2      <= 1'd0;
 
 
 
        //---------- 3rd Stage FF --------------------------
 
 
 
        txsync_start_reg3          <= 1'd0;
 
 
 
        txphinitdone_reg3    <= 1'd0;
 
 
 
        txdlysresetdone_reg3 <= 1'd0;
 
 
 
        txphaligndone_reg3   <= 1'd0;
 
 
 
        txsyncdone_reg3      <= 1'd0;
 
 
 
 
 
        end
 
        end
 
    else
 
    else
 
        begin
 
        begin
 
        //---------- 1st Stage FF --------------------------
 
        //---------- 1st Stage FF --------------------------
 
        gen3_reg1            <= SYNC_GEN3;
 
        gen3_reg1            <= SYNC_GEN3;
Line 281... Line 294... 
        rxdlysresetdone_reg2 <= rxdlysresetdone_reg1;
 
        rxdlysresetdone_reg2 <= rxdlysresetdone_reg1;
 
        rxphaligndone_m_reg2 <= rxphaligndone_m_reg1;
 
        rxphaligndone_m_reg2 <= rxphaligndone_m_reg1;
 
        rxphaligndone_s_reg2 <= rxphaligndone_s_reg1;
 
        rxphaligndone_s_reg2 <= rxphaligndone_s_reg1;
 
        rxsync_donem_reg2    <= rxsync_donem_reg1;
 
        rxsync_donem_reg2    <= rxsync_donem_reg1;
 
        rxsyncdone_reg2      <= rxsyncdone_reg1;
 
        rxsyncdone_reg2      <= rxsyncdone_reg1;
 
 
 
        //---------- 3rd Stage FF --------------------------
 
 
 
        txsync_start_reg3    <= txsync_start_reg2;
 
 
 
        txphinitdone_reg3    <= txphinitdone_reg2;
 
 
 
        txdlysresetdone_reg3 <= txdlysresetdone_reg2;
 
 
 
        txphaligndone_reg3   <= txphaligndone_reg2;
 
 
 
        txsyncdone_reg3      <= txsyncdone_reg2;
 
        end
 
        end
 
 
 
 
 
end
 
end
 
 
 
 
 
 
 
 
Line 339... Line 358... 
 
 
 
 
            //---------- TX Delay Soft Reset --------------- 
            //---------- TX Delay Soft Reset --------------- 
            FSM_TXSYNC_START :
 
            FSM_TXSYNC_START :
 
 
 
 
 
                begin
 
                begin
 
                fsm_tx      <= (((!txdlysresetdone_reg2 && txdlysresetdone_reg1) || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE)) ? FSM_TXPHINITDONE : FSM_TXSYNC_START);
 
                fsm_tx      <= (((!txdlysresetdone_reg3 && txdlysresetdone_reg2) || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE)) ? FSM_TXPHINITDONE : FSM_TXSYNC_START);
 
                txdlyen     <= 1'd0;
 
                txdlyen     <= 1'd0;
 
                txsync_done <= 1'd0;
 
                txsync_done <= 1'd0;
 
                end
 
                end
 
 
 
 
 
            //---------- Wait for TX Phase Init Done (Manual Mode Only)
 
            //---------- Wait for TX Phase Init Done (Manual Mode Only)
 
            FSM_TXPHINITDONE :
 
            FSM_TXPHINITDONE :
 
 
 
 
 
                begin
 
                begin
 
                fsm_tx      <= (((!txphinitdone_reg2 && txphinitdone_reg1) || (PCIE_TXSYNC_MODE == 1) || (!SYNC_ACTIVE_LANE)) ? FSM_TXSYNC_DONE1 : FSM_TXPHINITDONE);
 
                fsm_tx      <= (((!txphinitdone_reg3 && txphinitdone_reg2) || (PCIE_TXSYNC_MODE == 1) || (!SYNC_ACTIVE_LANE)) ? FSM_TXSYNC_DONE1 : FSM_TXPHINITDONE);
 
                txdlyen     <= 1'd0;
 
                txdlyen     <= 1'd0;
 
                txsync_done <= 1'd0;
 
                txsync_done <= 1'd0;
 
                end
 
                end
 
 
 
 
 
            //---------- Wait for TX Phase Alignment Done --
 
            //---------- Wait for TX Phase Alignment Done --
 
            FSM_TXSYNC_DONE1 :
 
            FSM_TXSYNC_DONE1 :
 
 
 
 
 
                begin
 
                begin
 
                if (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && !SYNC_SLAVE)
 
                if (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && !SYNC_SLAVE)
 
                   fsm_tx <= ((!txsyncdone_reg2 && txsyncdone_reg1)       || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
 
                   fsm_tx <= ((!txsyncdone_reg3 && txsyncdone_reg2)       || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
 
                else
 
                else
 
                   fsm_tx <= ((!txphaligndone_reg2 && txphaligndone_reg1) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
 
                   fsm_tx <= ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
 
 
 
 
 
                txdlyen     <= 1'd0;
 
                txdlyen     <= 1'd0;
 
                txsync_done <= 1'd0;
 
                txsync_done <= 1'd0;
 
                end
 
                end
 
 
 
 
 
            //---------- Wait for Master TX Delay Alignment Done 
            //---------- Wait for Master TX Delay Alignment Done 
            FSM_TXSYNC_DONE2 :
 
            FSM_TXSYNC_DONE2 :
 
 
 
 
 
                begin
 
                begin
 
                if ((!txphaligndone_reg2 && txphaligndone_reg1) || (!SYNC_ACTIVE_LANE) || SYNC_SLAVE || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1)) || (BYPASS_TXDELAY_ALIGN == 1))
 
                if ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) || SYNC_SLAVE || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1)) || (BYPASS_TXDELAY_ALIGN == 1))
 
                    begin
 
                    begin
 
                    fsm_tx      <= FSM_TXSYNC_IDLE;
 
                    fsm_tx      <= FSM_TXSYNC_IDLE;
 
                    txdlyen     <= !SYNC_SLAVE;
 
                    txdlyen     <= !SYNC_SLAVE;
 
                    txsync_done <= 1'd1;
 
                    txsync_done <= 1'd1;
 
                    end
 
                    end

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