| Line 47... |
Line 47... |
// PART OF THIS FILE AT ALL TIMES.
|
// PART OF THIS FILE AT ALL TIMES.
|
//
|
//
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Project : Series-7 Integrated Block for PCI Express
|
// Project : Series-7 Integrated Block for PCI Express
|
// File : cl_a7pcie_x4_pipe_user.v
|
// File : cl_a7pcie_x4_pipe_user.v
|
// Version : 1.9
|
// Version : 1.10
|
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
// Filename : pipe_user.v
|
// Filename : pipe_user.v
|
// Description : PIPE User Module for 7 Series Transceiver
|
// Description : PIPE User Module for 7 Series Transceiver
|
// Version : 15.3.3
|
// Version : 15.3.3
|
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
| Line 123... |
Line 123... |
output USER_RX_CONVERGE
|
output USER_RX_CONVERGE
|
|
|
);
|
);
|
|
|
//---------- Input Registers ---------------------------
|
//---------- Input Registers ---------------------------
|
reg pclk_sel_reg1;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg1;
|
reg resetovrd_start_reg1;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg1;
|
reg txresetdone_reg1;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1;
|
reg rxresetdone_reg1;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1;
|
reg txelecidle_reg1;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg1;
|
reg txcompliance_reg1;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg1;
|
reg rxcdrlock_reg1;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1;
|
reg rxvalid_reg1;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg1;
|
reg rxstatus_reg1;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg1;
|
reg rate_done_reg1;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg1;
|
reg rst_idle_reg1;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1;
|
reg rate_rxsync_reg1;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg1;
|
reg rate_idle_reg1;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1;
|
reg rate_gen3_reg1;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg1;
|
reg rxeq_adapt_done_reg1;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg1;
|
|
|
reg pclk_sel_reg2;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg2;
|
reg resetovrd_start_reg2;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg2;
|
reg txresetdone_reg2;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2;
|
reg rxresetdone_reg2;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2;
|
reg txelecidle_reg2;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg2;
|
reg txcompliance_reg2;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg2;
|
reg rxcdrlock_reg2;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2;
|
reg rxvalid_reg2;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg2;
|
reg rxstatus_reg2;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg2;
|
reg rate_done_reg2;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg2;
|
reg rst_idle_reg2;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2;
|
reg rate_rxsync_reg2;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg2;
|
reg rate_idle_reg2;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2;
|
reg rate_gen3_reg2;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg2;
|
reg rxeq_adapt_done_reg2;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg2;
|
|
|
//---------- Internal Signal ---------------------------
|
//---------- Internal Signal ---------------------------
|
reg [ 1:0] oobclk_cnt = 2'd0;
|
reg [ 1:0] oobclk_cnt = 2'd0;
|
reg [ 7:0] reset_cnt = 8'd127;
|
reg [ 7:0] reset_cnt = 8'd127;
|
reg [ 3:0] rxcdrlock_cnt = 4'd0;
|
reg [ 3:0] rxcdrlock_cnt = 4'd0;
|
