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// PART OF THIS FILE AT ALL TIMES.
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// PART OF THIS FILE AT ALL TIMES.
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_qpll_reset.v
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// File : cl_a7pcie_x4_qpll_reset.v
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// Version : 1.9
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// Version : 1.10
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Filename : qpll_reset.v
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// Filename : qpll_reset.v
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// Description : QPLL Reset Module for 7 Series Transceiver
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// Description : QPLL Reset Module for 7 Series Transceiver
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// Version : 11.4
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// Version : 11.4
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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output [ 3:0] QRST_FSM
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output [ 3:0] QRST_FSM
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);
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);
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//---------- Input Register ----------------------------
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//---------- Input Register ----------------------------
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reg mmcm_lock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
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reg [PCIE_LANE-1:0] cplllock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg1;
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reg [(PCIE_LANE-1)>>2:0]drp_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]drp_done_reg1;
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reg [(PCIE_LANE-1)>>2:0]qplllock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]qplllock_reg1;
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reg [ 1:0] rate_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg1;
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reg [PCIE_LANE-1:0] qpllreset_in_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllreset_in_reg1;
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reg [PCIE_LANE-1:0] qpllpd_in_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllpd_in_reg1;
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reg mmcm_lock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
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reg [PCIE_LANE-1:0] cplllock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg2;
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reg [(PCIE_LANE-1)>>2:0]drp_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]drp_done_reg2;
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reg [(PCIE_LANE-1)>>2:0]qplllock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]qplllock_reg2;
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reg [ 1:0] rate_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg2;
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reg [PCIE_LANE-1:0] qpllreset_in_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllreset_in_reg2;
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reg [PCIE_LANE-1:0] qpllpd_in_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllpd_in_reg2;
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//---------- Output Register --------------------------
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//---------- Output Register --------------------------
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reg ovrd = 1'd0;
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reg ovrd = 1'd0;
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reg qpllreset = 1'd1;
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reg qpllreset = 1'd1;
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reg qpllpd = 1'd0;
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reg qpllpd = 1'd0;
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reg [ 3:0] fsm = 2;
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reg [ 3:0] fsm = 2;
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//---------- FSM ---------------------------------------
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//---------- FSM ---------------------------------------
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localparam FSM_IDLE = 0;
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localparam FSM_IDLE = 1;
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localparam FSM_WAIT_LOCK = 1;
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localparam FSM_WAIT_LOCK = 2;
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localparam FSM_MMCM_LOCK = 2;
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localparam FSM_MMCM_LOCK = 3;
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localparam FSM_DRP_START_NOM = 3;
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localparam FSM_DRP_START_NOM = 4;
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localparam FSM_DRP_DONE_NOM = 4;
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localparam FSM_DRP_DONE_NOM = 5;
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localparam FSM_QPLLLOCK = 5;
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localparam FSM_QPLLLOCK = 6;
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localparam FSM_DRP_START_OPT = 6;
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localparam FSM_DRP_START_OPT = 7;
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localparam FSM_DRP_DONE_OPT = 7;
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localparam FSM_DRP_DONE_OPT = 8;
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localparam FSM_QPLL_RESET = 8;
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localparam FSM_QPLL_RESET = 9;
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localparam FSM_QPLLLOCK2 = 9;
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localparam FSM_QPLLLOCK2 = 10;
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localparam FSM_QPLL_PDRESET = 10;
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localparam FSM_QPLL_PDRESET = 11;
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localparam FSM_QPLL_PD = 11;
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localparam FSM_QPLL_PD = 12;
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//---------- Input FF ----------------------------------------------------------
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//---------- Input FF ----------------------------------------------------------
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always @ (posedge QRST_CLK)
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always @ (posedge QRST_CLK)
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