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// PART OF THIS FILE AT ALL TIMES.
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// PART OF THIS FILE AT ALL TIMES.
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_rxeq_scan.v
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// File : cl_a7pcie_x4_rxeq_scan.v
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// Version : 1.9
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// Version : 1.10
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Filename : rxeq_scan.v
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// Filename : rxeq_scan.v
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// Description : PIPE RX Equalization Eye Scan Module for 7 Series Transceiver
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// Description : PIPE RX Equalization Eye Scan Module for 7 Series Transceiver
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// Version : 18.0
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// Version : 18.0
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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output RXEQSCAN_ADAPT_DONE
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output RXEQSCAN_ADAPT_DONE
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);
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);
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//---------- Input Register ----------------------------
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//---------- Input Register ----------------------------
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reg [ 2:0] preset_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] preset_reg1;
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reg preset_valid_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg preset_valid_reg1;
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reg [ 3:0] txpreset_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txpreset_reg1;
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reg [17:0] txcoeff_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] txcoeff_reg1;
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reg new_txcoeff_req_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg new_txcoeff_req_reg1;
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reg [ 5:0] fs_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] fs_reg1;
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reg [ 5:0] lf_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] lf_reg1;
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reg [ 2:0] preset_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] preset_reg2;
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reg preset_valid_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg preset_valid_reg2;
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reg [ 3:0] txpreset_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txpreset_reg2;
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reg [17:0] txcoeff_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] txcoeff_reg2;
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reg new_txcoeff_req_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg new_txcoeff_req_reg2;
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reg [ 5:0] fs_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] fs_reg2;
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reg [ 5:0] lf_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] lf_reg2;
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//---------- Internal Signals --------------------------
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//---------- Internal Signals --------------------------
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reg adapt_done_cnt = 1'd0;
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reg adapt_done_cnt = 1'd0;
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//---------- Output Register ---------------------------
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//---------- Output Register ---------------------------
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