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Line 64... |
//
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//
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assign s_wb_transfer_ok_0 = (iv_wbs_burst_addr==0) & // START from INIT ADDR
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assign s_wb_transfer_ok_0 = (iv_wbs_burst_addr==0) & // START from INIT ADDR
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i_wbs_burst_cyc & i_wbs_burst_stb & i_wbs_burst_we & // WB Transfer strobes
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i_wbs_burst_cyc & i_wbs_burst_stb & i_wbs_burst_we & // WB Transfer strobes
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iv_wbs_burst_sel==8'hFF & // WB_SEL point to 64bit transfer
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iv_wbs_burst_sel==8'hFF & // WB_SEL point to 64bit transfer
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iv_wbs_burst_bte==2'b00 ; // WB Burst Transfer type check (Linear Burst)
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iv_wbs_burst_bte==2'b00 ; // WB Burst Transfer type check (Linear Burst)
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//FIX
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/*assign s_wb_transfer_master_hold = (iv_wbs_burst_addr==0) & // START from INIT ADDR
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assign s_wb_transfer_master_hold = (iv_wbs_burst_addr==0) & // START from INIT ADDR
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i_wbs_burst_cyc & !i_wbs_burst_stb & i_wbs_burst_we & // WB Transfer strobes (MASTER STALL case)
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i_wbs_burst_cyc & !i_wbs_burst_stb & i_wbs_burst_we & // WB Transfer strobes (MASTER STALL case)
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iv_wbs_burst_sel==8'hFF & // WB_SEL point to 64bit transfer
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iv_wbs_burst_sel==8'hFF & // WB_SEL point to 64bit transfer
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iv_wbs_burst_bte==2'b00 ; // WB Burst Transfer type check (Linear Burst)*/
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iv_wbs_burst_bte==2'b00 ; // WB Burst Transfer type check (Linear Burst)*/
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// WB stuff:
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// WB stuff:
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assign o_wbs_burst_ack = s_wb_transfer_ok_0;
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assign o_wbs_burst_ack = s_wb_transfer_ok_0;
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assign o_wbs_burst_rty = 0; // for now no WB Retry func, only WB_ERR for now
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assign o_wbs_burst_rty = 0; // for now no WB Retry func, only WB_ERR for now
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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//
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//
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always @ (posedge i_clk or posedge i_rst)
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//always @ (posedge i_clk or posedge i_rst)
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always @ (posedge i_clk)
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begin : TEST_CHECK_DATA_OUT
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begin : TEST_CHECK_DATA_OUT
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//
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//
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o_test_check_data_ena <= s_wb_transfer_ok_0;
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o_test_check_data_ena <= s_wb_transfer_ok_0;
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ov_test_check_data <= iv_wbs_burst_data;
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ov_test_check_data <= iv_wbs_burst_data;
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