| Line 140... |
Line 140... |
signal sv_test_gen_fifo_data : std_logic_vector(63 downto 0);
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signal sv_test_gen_fifo_data : std_logic_vector(63 downto 0);
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signal s_test_gen_fifo_rd : std_logic;
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signal s_test_gen_fifo_rd : std_logic;
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signal s_test_gen_fifo_full : std_logic;
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signal s_test_gen_fifo_full : std_logic;
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signal s_test_gen_fifo_empty : std_logic;
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signal s_test_gen_fifo_empty : std_logic;
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signal s_test_gen_fifo_prog_full : std_logic;
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signal s_test_gen_fifo_prog_full : std_logic;
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signal iv_test_gen_status : std_logic_vector( 31 downto 0 );
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signal rstp : std_logic;
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signal dmar : std_logic;
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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begin
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begin
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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--
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--
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-- Instaniate WB_CFG_SLAVE
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-- Instaniate WB_CFG_SLAVE
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| Line 181... |
Line 184... |
ov_test_gen_size => sv_test_gen_size,
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ov_test_gen_size => sv_test_gen_size,
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ov_test_gen_cnt1 => sv_test_gen_cnt1,
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ov_test_gen_cnt1 => sv_test_gen_cnt1,
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ov_test_gen_cnt2 => sv_test_gen_cnt2,
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ov_test_gen_cnt2 => sv_test_gen_cnt2,
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--
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--
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-- STATUS Input
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-- STATUS Input
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iv_test_gen_status => iv_test_gen_status,
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iv_test_gen_bl_wr => sv_test_gen_bl_wr
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iv_test_gen_bl_wr => sv_test_gen_bl_wr
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);
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);
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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--
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--
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-- Instaniate TEST_GEN
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-- Instaniate TEST_GEN
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| Line 220... |
Line 224... |
PORT MAP
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PORT MAP
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(
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(
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--
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--
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-- SYS_CON
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-- SYS_CON
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clk => i_clk,
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clk => i_clk,
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rst => i_rst,
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rst => rstp,
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--
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--
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-- DATA_IN
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-- DATA_IN
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din => sv_di_data,
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din => sv_di_data,
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wr_en => s_di_data_we,
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wr_en => s_di_data_we,
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--
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--
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| Line 278... |
Line 282... |
-- define TEST_GEN.di_flag_paf like TEST_GEN_FIFO.prog_full
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-- define TEST_GEN.di_flag_paf like TEST_GEN_FIFO.prog_full
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s_di_flag_paf <= not s_test_gen_fifo_prog_full;
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s_di_flag_paf <= not s_test_gen_fifo_prog_full;
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-- define TEST_GEN.di_start like TEST_GEN.sv_test_gen_ctrl[1] ( 1-> RSVD )
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-- define TEST_GEN.di_start like TEST_GEN.sv_test_gen_ctrl[1] ( 1-> RSVD )
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s_di_start <= sv_test_gen_ctrl(5);
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s_di_start <= sv_test_gen_ctrl(5);
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-- define TEST_GEN.di_fifo_rst - it is RST_n signal
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-- define TEST_GEN.di_fifo_rst - it is RST_n signal
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s_di_fifo_rst <= not i_rst;
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s_di_fifo_rst <= not rstp;
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rstp <= i_rst or sv_test_gen_ctrl(0) after 1 ns when rising_edge( i_clk );
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iv_test_gen_status(0) <= '1';
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iv_test_gen_status(1) <= '0';
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iv_test_gen_status(2) <= s_test_gen_fifo_empty;
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iv_test_gen_status(3) <= s_test_gen_fifo_prog_full;
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iv_test_gen_status(4) <= s_test_gen_fifo_full;
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iv_test_gen_status(5) <= '0';
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iv_test_gen_status(6) <= '0';
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iv_test_gen_status(7) <= '0';
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iv_test_gen_status(8) <= sv_test_gen_ctrl(5);
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iv_test_gen_status(9) <= dmar;
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iv_test_gen_status(10) <= rstp;
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iv_test_gen_status(11) <= '0';
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iv_test_gen_status(12) <= '0';
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iv_test_gen_status(13) <= '0';
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iv_test_gen_status(14) <= '0';
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iv_test_gen_status(15) <= '0';
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iv_test_gen_status( 31 downto 16 ) <= (others=>'0');
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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--
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--
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-- MODULE OUTPUTs routing:
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-- MODULE OUTPUTs routing:
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--
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--
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-- DMAR WB IRQ deal
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-- DMAR WB IRQ deal
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o_wbs_irq_dmar <= s_test_gen_fifo_prog_full; -- (DS: 512 слов заполнили - взевели dmar)
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dmar <= s_test_gen_fifo_prog_full or sv_test_gen_ctrl(14); -- (DS: 512 слов заполнили - взевели dmar)
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o_wbs_irq_dmar <= dmar;
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-- WB IRQ deal
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-- WB IRQ deal
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o_wbs_irq_0 <= '0'; -- No EVENTs for now
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o_wbs_irq_0 <= '0'; -- No EVENTs for now
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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end rtl;
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end rtl;
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