| Line 30... |
Line 30... |
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package test_pkg is
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package test_pkg is
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--! Initialising
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--! Initialising
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procedure test_init(
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procedure test_init(
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fname: in string --! имя файла отчёта
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fname: in string --! file name for report
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);
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);
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--! Finished
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--! Finished
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procedure test_close;
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procedure test_close;
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--! Read registers
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procedure test_read_reg (
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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);
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--! Start DMA with incorrect descriptor
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--! Start DMA with incorrect descriptor
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procedure test_dsc_incorrect (
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procedure test_dsc_incorrect (
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signal cmd: out bh_cmd; --! команда
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! ответ
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signal ret: in bh_ret --! answer
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);
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);
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--! Start DMA for one block 4 kB
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--! Start DMA for one block 4 kB
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procedure test_read_4kb (
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procedure test_read_4kb (
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signal cmd: out bh_cmd; --! команда
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! ответ
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signal ret: in bh_ret --! answer
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);
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);
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--! Read block_test_check 8 kB
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--! Read block_test_check 8 kB
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procedure test_adm_read_8kb (
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procedure test_adm_read_8kb (
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signal cmd: out bh_cmd; --! команда
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! ответ
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signal ret: in bh_ret --! answer
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);
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);
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----! Проверка обращений к блоку MAIN
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----! Проверка обращений к блоку MAIN
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--procedure test_block_main (
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--procedure test_block_main (
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-- signal cmd: out bh_cmd; --! команда
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-- signal cmd: out bh_cmd; --! command
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-- signal ret: in bh_ret --! ответ
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-- signal ret: in bh_ret --! answer
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-- );
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-- );
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--
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--
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----! Чтение 16 кБ с использованием двух блоков дескрипторов
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----! Чтение 16 кБ с использованием двух блоков дескрипторов
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--procedure test_adm_read_16kb (
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--procedure test_adm_read_16kb (
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-- signal cmd: out bh_cmd; --! команда
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-- signal cmd: out bh_cmd; --! command
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-- signal ret: in bh_ret --! ответ
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-- signal ret: in bh_ret --! answer
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-- );
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-- );
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--
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--
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--! Запись 16 кБ с использованием двух блоков дескрипторов
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--! Запись 16 кБ с использованием двух блоков дескрипторов
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procedure test_adm_write_16kb (
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procedure test_adm_write_16kb (
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signal cmd: out bh_cmd; --! команда
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! ответ
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signal ret: in bh_ret --! answer
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);
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);
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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--
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--
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--
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--
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procedure test_num_1(
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procedure test_num_1(
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signal cmd: out bh_cmd; --! команда
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! ответ
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signal ret: in bh_ret --! answer
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);
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);
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procedure test_num_2(
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procedure test_num_2(
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signal cmd: out bh_cmd; --! команда
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! ответ
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signal ret: in bh_ret --! answer
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);
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);
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-- ==> TEST_CHECK.WB_CFG_SLAVE
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-- ==> TEST_CHECK.WB_CFG_SLAVE
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procedure test_wb_1(
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procedure test_wb_1(
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signal cmd: out bh_cmd; --! команда
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! ответ
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signal ret: in bh_ret --! answer
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);
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);
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-- ==> TEST_GEN.WB_CFG_SLAVE
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-- ==> TEST_GEN.WB_CFG_SLAVE
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procedure test_wb_2(
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procedure test_wb_2(
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signal cmd: out bh_cmd; --! команда
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! ответ
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signal ret: in bh_ret --! answer
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);
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);
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end package test_pkg;
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end package test_pkg;
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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package body test_pkg is
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package body test_pkg is
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| Line 149... |
Line 154... |
end if;
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end if;
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end test_close;
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end test_close;
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--! Read registers
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procedure test_read_reg (
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! answer
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)
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is
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variable adr : std_logic_vector( 31 downto 0 );
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variable data1 : std_logic_vector( 31 downto 0 );
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variable data2 : std_logic_vector( 31 downto 0 );
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variable str : line;
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begin
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write( str, string'("TEST_READ_REG" ));
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writeline( log, str );
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block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE
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wait for 100 ns;
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--block_read( cmd, ret, 4, 23, x"0000A400" ); -- LOCAL_ADR
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wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data1 ); -- read block id
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wb_block_check_read( cmd, ret, REG_BLOCK_ID, data2 ); -- read block id
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write( str, string'("BLOCK 0 ID: " )); hwrite( str, data1( 15 downto 0 ) );
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writeline( log, str );
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write( str, string'("BLOCK 1 ID: " )); hwrite( str, data2( 15 downto 0 ) );
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writeline( log, str );
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wb_read( cmd, ret, 16#1000#, data1 );
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wb_read( cmd, ret, 16#3000#, data1 );
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write( str, string'("0x1000: " )); hwrite( str, data1( 15 downto 0 ) );
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writeline( log, str );
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write( str, string'("0x3000: " )); hwrite( str, data2( 15 downto 0 ) );
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writeline( log, str );
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block_write( cmd, ret, 0, 8, x"00000000" ); -- BRD_MODE
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wait for 100 ns;
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block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE
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wait for 100 ns;
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wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data1 ); -- read block id
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wb_block_check_read( cmd, ret, REG_BLOCK_ID, data2 ); -- read block id
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write( str, string'("BLOCK 0 ID: " )); hwrite( str, data1( 15 downto 0 ) );
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writeline( log, str );
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write( str, string'("BLOCK 1 ID: " )); hwrite( str, data2( 15 downto 0 ) );
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writeline( log, str );
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end test_read_reg;
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--! Start DMA with incorrect descriptor
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--! Start DMA with incorrect descriptor
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procedure test_dsc_incorrect (
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procedure test_dsc_incorrect (
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signal cmd: out bh_cmd; --! команда
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! ответ
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signal ret: in bh_ret --! answer
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)
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)
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is
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is
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variable adr : std_logic_vector( 31 downto 0 );
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variable adr : std_logic_vector( 31 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
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| Line 207... |
Line 271... |
end test_dsc_incorrect;
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end test_dsc_incorrect;
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--! Start DMA for one block 4 kB
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--! Start DMA for one block 4 kB
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procedure test_read_4kb (
|
procedure test_read_4kb (
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signal cmd: out bh_cmd; --! команда
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! ответ
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signal ret: in bh_ret --! answer
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)
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)
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is
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is
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variable adr : std_logic_vector( 31 downto 0 );
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variable adr : std_logic_vector( 31 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
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| Line 359... |
Line 423... |
end test_read_4kb;
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end test_read_4kb;
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--! Read block_test_check 8 kB
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--! Read block_test_check 8 kB
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procedure test_adm_read_8kb (
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procedure test_adm_read_8kb (
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signal cmd: out bh_cmd; --! команда
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signal cmd: out bh_cmd; --! command
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signal ret: in bh_ret --! ответ
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signal ret: in bh_ret --! answer
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)
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)
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is
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is
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|
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variable adr : std_logic_vector( 31 downto 0 );
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variable adr : std_logic_vector( 31 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
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| Line 531... |
Line 595... |
end test_adm_read_8kb;
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end test_adm_read_8kb;
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--
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--
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--
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--
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----! Проверка обращений к блоку MAIN
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----! Проверка обращений к блоку MAIN
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--procedure test_block_main (
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--procedure test_block_main (
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-- signal cmd: out bh_cmd; --! команда
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-- signal cmd: out bh_cmd; --! command
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-- signal ret: in bh_ret --! ответ
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-- signal ret: in bh_ret --! answer
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-- )
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-- )
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--is
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--is
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--
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--
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--variable adr : std_logic_vector( 31 downto 0 );
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--variable adr : std_logic_vector( 31 downto 0 );
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--variable data : std_logic_vector( 31 downto 0 );
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--variable data : std_logic_vector( 31 downto 0 );
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| Line 616... |
Line 680... |
--
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--
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--
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--
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--
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--
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----! Чтение 16 кБ с использованием двух блоков дескрипторов
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----! Чтение 16 кБ с использованием двух блоков дескрипторов
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--procedure test_adm_read_16kb (
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--procedure test_adm_read_16kb (
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-- signal cmd: out bh_cmd; --! команда
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-- signal cmd: out bh_cmd; --! command
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-- signal ret: in bh_ret --! ответ
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-- signal ret: in bh_ret --! answer
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-- )
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-- )
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--is
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--is
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--
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--
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--variable adr : std_logic_vector( 31 downto 0 );
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--variable adr : std_logic_vector( 31 downto 0 );
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--variable data : std_logic_vector( 31 downto 0 );
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--variable data : std_logic_vector( 31 downto 0 );
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| Line 867... |
Line 931... |
--
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--
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--
|
--
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--
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--
|
--! Запись 16 кБ с использованием двух блоков дескрипторов
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--! Запись 16 кБ с использованием двух блоков дескрипторов
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procedure test_adm_write_16kb (
|
procedure test_adm_write_16kb (
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signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
)
|
)
|
is
|
is
|
|
|
variable adr : std_logic_vector( 31 downto 0 );
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variable adr : std_logic_vector( 31 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
|
| Line 1296... |
Line 1360... |
---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
--
|
--
|
-- My procedure for test Updated Design (test_read_4kb like refenernce)
|
-- My procedure for test Updated Design (test_read_4kb like refenernce)
|
--
|
--
|
procedure test_num_1 (
|
procedure test_num_1 (
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
) is
|
) is
|
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
|
variable str : line;
|
variable str : line;
|
| Line 1433... |
Line 1497... |
end test_num_1;
|
end test_num_1;
|
--
|
--
|
--
|
--
|
--
|
--
|
procedure test_num_2 (
|
procedure test_num_2 (
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
) is
|
) is
|
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
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variable data64 : std_logic_vector( 63 downto 0 );
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variable data64 : std_logic_vector( 63 downto 0 );
|
| Line 1584... |
Line 1648... |
--
|
--
|
-- My procedure for test WB stuff in Design:
|
-- My procedure for test WB stuff in Design:
|
-- ==> TEST_CHECK.WB_CFG_SLAVE
|
-- ==> TEST_CHECK.WB_CFG_SLAVE
|
--
|
--
|
procedure test_wb_1 (
|
procedure test_wb_1 (
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
) is
|
) is
|
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable data32 : std_logic_vector( 31 downto 0 );
|
variable data32 : std_logic_vector( 31 downto 0 );
|
variable data64 : std_logic_vector( 63 downto 0 );
|
variable data64 : std_logic_vector( 63 downto 0 );
|
| Line 1747... |
Line 1811... |
--
|
--
|
-- My procedure for test WB stuff in Design:
|
-- My procedure for test WB stuff in Design:
|
-- ==> TEST_GEN.WB_CFG_SLAVE
|
-- ==> TEST_GEN.WB_CFG_SLAVE
|
--
|
--
|
procedure test_wb_2 (
|
procedure test_wb_2 (
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! command
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! answer
|
) is
|
) is
|
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable data32 : std_logic_vector( 31 downto 0 );
|
variable data32 : std_logic_vector( 31 downto 0 );
|
variable data64 : std_logic_vector( 63 downto 0 );
|
variable data64 : std_logic_vector( 63 downto 0 );
|
