| Line 442... |
Line 442... |
variable str : line;
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variable str : line;
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variable error : integer:=0;
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variable error : integer:=0;
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variable dma_complete : integer;
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variable dma_complete : integer;
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variable status : std_logic_vector( 31 downto 0 );
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variable reg_block_wr : std_logic_vector( 31 downto 0 );
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begin
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begin
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write( str, string'("TEST_ADM_READ_8KB" ));
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write( str, string'("TEST_ADM_READ_8KB" ));
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writeline( log, str );
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writeline( log, str );
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| Line 471... |
Line 474... |
int_mem_write( cmd, ret, x"001001F8", x"00000000" );
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int_mem_write( cmd, ret, x"001001F8", x"00000000" );
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int_mem_write( cmd, ret, x"001001FC", x"D6644953" );
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int_mem_write( cmd, ret, x"001001FC", x"D6644953" );
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---- Программирование канала DMA ----
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---- Программирование канала DMA ----
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block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE
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block_write( cmd, ret, 5, 8, x"00000027" ); -- DMA_MODE
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block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
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block_write( cmd, ret, 5, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
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block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
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block_write( cmd, ret, 5, 20, x"00100000" ); -- PCI_ADRL
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block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
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block_write( cmd, ret, 5, 21, x"00100000" ); -- PCI_ADRH
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block_write( cmd, ret, 4, 23, TEST_GEN_WB_BURST_SLAVE ); -- LOCAL_ADR
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block_write( cmd, ret, 5, 23, TEST_GEN_WB_BURST_SLAVE ); -- LOCAL_ADR
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wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000001" ); -- reset
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wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000001" ); -- reset
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wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000000" );
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wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000000" );
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wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data ); -- read block id
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wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data ); -- read block id
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Line 491... |
hwrite( str, data );
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hwrite( str, data );
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writeline( log, str );
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writeline( log, str );
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wb_block_gen_write( cmd, ret, REG_TEST_GEN_SIZE, x"00000001" ); -- size of block = 4 kByte
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wb_block_gen_write( cmd, ret, REG_TEST_GEN_SIZE, x"00000001" ); -- size of block = 4 kByte
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block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
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block_write( cmd, ret, 5, 9, x"00000001" ); -- DMA_CTRL - START
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wb_block_gen_read( cmd, ret, REG_TEST_GEN_STATUS, status ); -- read status
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write( str, string'("WB_GEN_STATUS: " )); hwrite( str, status( 31 downto 0 ) ); writeline( log, str );
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wb_block_gen_read( cmd, ret, REG_TEST_GEN_BL_WR, reg_block_wr ); -- read block_wr
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write( str, string'("WB_GEN_BL_WR: " )); hwrite( str, reg_block_wr( 31 downto 0 ) ); writeline( log, str );
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wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A0" ); -- start test sequence
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wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A0" ); -- start test sequence
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wait for 20 us;
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wait for 20 us;
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block_read( cmd, ret, 4, 16, data ); -- STATUS
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block_read( cmd, ret, 5, 16, data ); -- STATUS
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write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
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write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
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if( data( 8 )='1' ) then
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if( data( 8 )='1' ) then
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write( str, string'(" - descriptor is correct" ));
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write( str, string'(" - descriptor is correct" ));
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else
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else
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| Line 512... |
Line 521... |
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---- Ожидание завершения DMA ----
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---- Ожидание завершения DMA ----
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dma_complete := 0;
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dma_complete := 0;
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for ii in 0 to 100 loop
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for ii in 0 to 100 loop
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block_read( cmd, ret, 4, 16, data ); -- STATUS
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block_read( cmd, ret, 5, 16, data ); -- STATUS
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write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
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write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
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if( data(5)='1' ) then
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if( data(5)='1' ) then
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write( str, string'(" - DMA finished " ));
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write( str, string'(" - DMA finished " ));
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dma_complete := 1;
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dma_complete := 1;
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block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - reset EOT
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block_write( cmd, ret, 5, 16#11#, x"00000010" ); -- FLAG_CLR - reset EOT
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end if;
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end if;
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writeline( log, str );
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writeline( log, str );
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if( dma_complete=1 ) then
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if( dma_complete=1 ) then
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| Line 541... |
Line 550... |
error:=error+1;
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error:=error+1;
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end if;
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end if;
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end if;
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end if;
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wb_block_gen_read( cmd, ret, REG_TEST_GEN_STATUS, status ); -- read status
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write( str, string'("WB_GEN_STATUS: " )); hwrite( str, status( 31 downto 0 ) ); writeline( log, str );
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wb_block_gen_read( cmd, ret, REG_TEST_GEN_BL_WR, reg_block_wr ); -- read block_wr
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write( str, string'("WB_GEN_BL_WR: " )); hwrite( str, reg_block_wr( 31 downto 0 ) ); writeline( log, str );
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for ii in 0 to 3 loop
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for ii in 0 to 3 loop
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block_read( cmd, ret, 4, 16, data ); -- STATUS
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block_read( cmd, ret, 5, 16, data ); -- STATUS
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write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
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write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
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writeline( log, str );
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writeline( log, str );
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wait for 500 ns;
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wait for 500 ns;
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end loop;
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end loop;
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block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
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block_write( cmd, ret, 5, 9, x"00000000" ); -- DMA_CTRL - STOP
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write( str, string'(" Block 0 - read: " ));
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write( str, string'(" Block 0 - read: " ));
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writeline( log, str );
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writeline( log, str );
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for ii in 0 to 15 loop
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for ii in 0 to 15 loop
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