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Rev 38 |
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Enabled=1
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[file:.\src\testbench\ahdl\tx.awf]
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[file:.\src\testbench\ahdl\tx.awf]
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[file:.\src\testbench\ahdl\run_ahdl.tcl]
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[file:.\src\testbench\ahdl\run_ahdl.tcl]
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Enabled=1
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[file:.\src\pcie_src\components\pcie_core\pcie_core64_wishbone_m8.vhd]
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Enabled=0
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[file:.\src\testbench\log\console_test_adm_read_8kb.log]
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[file:.\src\testbench\log\console_test_dsc_incorrect.log]
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[file:.\src\testbench\log\console_test_read 4 kB.log]
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[file:.\src\testbench\log\console_test_read_4kB.log]
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[file:.\src\testbench\log\file_id_0.log]
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[file:.\src\testbench\log\file_id_1.log]
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Enabled=1
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[file:.\src\testbench\log\file_id_2.log]
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Enabled=1
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[file:.\src\testbench\log\global_tc_summary.log]
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[file:.\synthesis\sp605_lx45t_wishbone.vhd]
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LIB=sp605_lx45t_wishbone_post_synthesis
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SIM.POST.INCLUDED=1
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SIM.FUNC.INCLUDED=0
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SIM.POST.AUTO=1
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SIM.POST.INDEX=0
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[file:.\src\DESIGN_STATUS\2013_07_26_01_18\ComputerInformation.txt]
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[file:.\src\DESIGN_STATUS\2013_07_26_01_18\DesignInformation.txt]
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Enabled=1
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[file:.\src\DESIGN_STATUS\2013_07_26_01_18\DesignFiles.txt]
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Enabled=1
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[file:.\src\DESIGN_STATUS\2013_07_26_01_18\LibrariesList.txt]
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Enabled=1
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[file:.\src\DESIGN_STATUS\2013_07_26_01_18\synthesis_synthesis.dfml]
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Enabled=1
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[file:.\src\DESIGN_STATUS\2013_07_26_01_18\implement_ver1_rev1_implementation.dfml]
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Enabled=1
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