URL
https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 10 |
Rev 38 |
Line 218... |
Line 218... |
Enabled=1
|
Enabled=1
|
[file:.\src\testbench\ahdl\tx.awf]
|
[file:.\src\testbench\ahdl\tx.awf]
|
Enabled=1
|
Enabled=1
|
[file:.\src\testbench\ahdl\run_ahdl.tcl]
|
[file:.\src\testbench\ahdl\run_ahdl.tcl]
|
Enabled=1
|
Enabled=1
|
|
[file:.\src\pcie_src\components\pcie_core\pcie_core64_wishbone_m8.vhd]
|
|
Enabled=0
|
|
[file:.\src\testbench\log\console_test_adm_read_8kb.log]
|
|
Enabled=1
|
|
[file:.\src\testbench\log\console_test_dsc_incorrect.log]
|
|
Enabled=1
|
|
[file:.\src\testbench\log\console_test_read 4 kB.log]
|
|
Enabled=1
|
|
[file:.\src\testbench\log\console_test_read_4kB.log]
|
|
Enabled=1
|
|
[file:.\src\testbench\log\file_id_0.log]
|
|
Enabled=1
|
|
[file:.\src\testbench\log\file_id_1.log]
|
|
Enabled=1
|
|
[file:.\src\testbench\log\file_id_2.log]
|
|
Enabled=1
|
|
[file:.\src\testbench\log\global_tc_summary.log]
|
|
Enabled=1
|
|
[file:.\synthesis\sp605_lx45t_wishbone.vhd]
|
|
Enabled=1
|
|
LIB=sp605_lx45t_wishbone_post_synthesis
|
|
SIM.POST.INCLUDED=1
|
|
SIM.FUNC.INCLUDED=0
|
|
SIM.POST.AUTO=1
|
|
SIM.POST.INDEX=0
|
|
[file:.\src\DESIGN_STATUS\2013_07_26_01_18\ComputerInformation.txt]
|
|
Enabled=1
|
|
[file:.\src\DESIGN_STATUS\2013_07_26_01_18\DesignInformation.txt]
|
|
Enabled=1
|
|
[file:.\src\DESIGN_STATUS\2013_07_26_01_18\DesignFiles.txt]
|
|
Enabled=1
|
|
[file:.\src\DESIGN_STATUS\2013_07_26_01_18\LibrariesList.txt]
|
|
Enabled=1
|
|
[file:.\src\DESIGN_STATUS\2013_07_26_01_18\synthesis_synthesis.dfml]
|
|
Enabled=1
|
|
[file:.\src\DESIGN_STATUS\2013_07_26_01_18\implement_ver1_rev1_implementation.dfml]
|
|
Enabled=1
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.