| Line 33... |
Line 33... |
REFRESH_FLOW=1
|
REFRESH_FLOW=1
|
FAMILY=Xilinx12x VIRTEX5
|
FAMILY=Xilinx12x VIRTEX5
|
RUN_MODE_SYNTH=0
|
RUN_MODE_SYNTH=0
|
VerilogDirsChanged=1
|
VerilogDirsChanged=1
|
WireDelay=2
|
WireDelay=2
|
NoTchkMsg=0
|
NoTchkMsg=1
|
NoTimingChecks=0
|
NoTimingChecks=1
|
HESPrepare=0
|
HESPrepare=0
|
EnableXtrace=0
|
EnableXtrace=0
|
SplitNetVectors=0
|
SplitNetVectors=0
|
StackMemorySize=32
|
StackMemorySize=32
|
RetvalMemorySize=32
|
RetvalMemorySize=32
|
| Line 57... |
Line 57... |
CoverAction=Continue
|
CoverAction=Continue
|
ReportDroppedCoverEvaluations=0
|
ReportDroppedCoverEvaluations=0
|
ReportActivatedCoverEvaluations=0
|
ReportActivatedCoverEvaluations=0
|
fileopeninsrc=1
|
fileopeninsrc=1
|
fileopenfolder=E:\prog\ds_dma_project\sp605_lx45t_wishbone
|
fileopenfolder=E:\prog\ds_dma_project\sp605_lx45t_wishbone
|
|
DisableVitalMsg=1
|
|
VitalAccel=1
|
|
VitalGlitches=1
|
|
DisableIEEEWarnings=1
|
|
|
[LocalVerilogSets]
|
[LocalVerilogSets]
|
EnableSLP=1
|
EnableSLP=1
|
EnableDebug=1
|
EnableDebug=1
|
VerilogLanguage=4
|
VerilogLanguage=4
|
| Line 76... |
Line 80... |
AdditionalOptions=
|
AdditionalOptions=
|
MonitoringOfEventsUDP=0
|
MonitoringOfEventsUDP=0
|
DisablePulseError=0
|
DisablePulseError=0
|
HasInitialRegsValue=0
|
HasInitialRegsValue=0
|
InitialRegsValue=X
|
InitialRegsValue=X
|
PriorityLibNames=ovi_unisim;ovi_xilinxcorelib;ovi_unimacro;
|
|
|
|
[LocalVhdlSets]
|
[LocalVhdlSets]
|
CompileWithDebug=1
|
CompileWithDebug=1
|
|
DisableVHDL87Key=0
|
|
EnableVHDL93Key=0
|
|
EnableVHDL2002Key=1
|
|
EnableVHDL2006Key=0
|
|
EnableVHDL2008Key=0
|
|
NetlistCompilation=1
|
|
Syntax RelaxLRM=0
|
|
MaxErrorsKey=100
|
|
OptimizationLevel=3
|
|
DisableRangeChecks=0
|
|
ProtectLevel=0
|
|
AdditionalOptions=
|
|
IncrementalCompilation=0
|
|
ReorderOnFirstRebuild=1
|
|
ElaborationAfterCompilation=0
|
|
PrintErrWarnOnly=0
|
|
GenMultiplatformLib=0
|
|
VhdlChangeEvalAsynchronous=0
|
|
VhdlDisableAssertionsProcessing=0
|
|
|
[$LibMap$]
|
[$LibMap$]
|
sp605_lx45t_wishbone=.
|
sp605_lx45t_wishbone=.
|
Active_lib=VIRTEX5
|
Active_lib=VIRTEX5
|
xilinxun=VIRTEX5
|
xilinxun=VIRTEX5
|
| Line 103... |
Line 125... |
impl_opt(dont_run_fit)=0
|
impl_opt(dont_run_fit)=0
|
impl_opt(dont_run_bitgen)=1
|
impl_opt(dont_run_bitgen)=1
|
|
|
[HierarchyViewer]
|
[HierarchyViewer]
|
SortInfo=u
|
SortInfo=u
|
HierarchyInformation=cl_s6pcie_m2|rtl|0 stend_sp605_wishbone|stend_sp605_wishbone|0
|
HierarchyInformation=stend_sp605_wishbone|stend_sp605_wishbone|0
|
ShowHide=ShowTopLevel
|
ShowHide=ShowTopLevel
|
Selected=
|
Selected=
|
|
|
[DefineMacro]
|
[DefineMacro]
|
Global=
|
Global=
|
|
|
[Verilog Library]
|
|
ovi_unimacro=
|
|
ovi_unisim=
|
|
ovi_xilinxcorelib=
|
|
|
|
[Folders]
|
[Folders]
|
Name3=Makefiles
|
Name3=Makefiles
|
Directory3=e:\prog\ds_dma_project\trunk\projects\sp605_lx45t_wishbone\
|
Directory3=e:\prog\ds_dma_project\trunk\projects\sp605_lx45t_wishbone\
|
Extension3=mak
|
Extension3=mak
|
Name4=Memory
|
Name4=Memory
|
| Line 157... |
Line 174... |
testbench\modelsim\required_tests=1
|
testbench\modelsim\required_tests=1
|
testbench\modelsim\required_tests\test0=1
|
testbench\modelsim\required_tests\test0=1
|
testbench\modelsim\required_tests\test0\zz_do=1
|
testbench\modelsim\required_tests\test0\zz_do=1
|
testbench\ahdl=1
|
testbench\ahdl=1
|
top=1
|
top=1
|
log=1
|
|
wishbone=1
|
wishbone=1
|
wishbone\block_test_check=1
|
wishbone\block_test_check=1
|
wishbone\block_test_generate=1
|
wishbone\block_test_generate=1
|
wishbone\cross=1
|
wishbone\cross=1
|
wishbone\doc=1
|
wishbone\doc=1
|
| Line 177... |
Line 193... |
wishbone\testbecnh\dev_test_gen\sim=1
|
wishbone\testbecnh\dev_test_gen\sim=1
|
wishbone\testbecnh\dev_test_gen\sim\zz_do=1
|
wishbone\testbecnh\dev_test_gen\sim\zz_do=1
|
wishbone\testbecnh\dev_wb_cross=1
|
wishbone\testbecnh\dev_wb_cross=1
|
wishbone\testbecnh\dev_wb_cross\sim=1
|
wishbone\testbecnh\dev_wb_cross\sim=1
|
wishbone\testbecnh\dev_wb_cross\sim\zz_do=1
|
wishbone\testbecnh\dev_wb_cross\sim\zz_do=1
|
|
testbench\log=1
|
|
|
|
[Verilog Library]
|
|
ovi_unimacro=
|
|
ovi_unisim=
|
|
ovi_xilinxcorelib=
|
|
|
[Files]
|
[Files]
|
pcie_src\components\block_main/block_pe_main.vhd=-1
|
pcie_src\components\block_main/block_pe_main.vhd=-1
|
pcie_src\components\coregen/ctrl_fifo64x34fw.ngc=-1
|
pcie_src\components\coregen/ctrl_fifo64x34fw.ngc=-1
|
pcie_src\components\coregen/ctrl_fifo64x34fw.vhd=-1
|
pcie_src\components\coregen/ctrl_fifo64x34fw.vhd=-1
|
| Line 337... |
Line 359... |
testbench\modelsim\required_tests\test0\zz_do/setup_sim.do=-1
|
testbench\modelsim\required_tests\test0\zz_do/setup_sim.do=-1
|
testbench\ahdl/test_gen.awf=-1
|
testbench\ahdl/test_gen.awf=-1
|
testbench\ahdl/pb_wishbone.awf=-1
|
testbench\ahdl/pb_wishbone.awf=-1
|
testbench\ahdl/rx.awf=-1
|
testbench\ahdl/rx.awf=-1
|
testbench\ahdl/tx.awf=-1
|
testbench\ahdl/tx.awf=-1
|
|
testbench\ahdl/run_ahdl.tcl=-1
|
top/sp605_lx45t_wishbone.ucf=-1
|
top/sp605_lx45t_wishbone.ucf=-1
|
top/sp605_lx45t_wishbone_sopc_wb.vhd=-1
|
top/sp605_lx45t_wishbone_sopc_wb.vhd=-1
|
top/sp605_lx45t_wishbone.vhd=-1
|
top/sp605_lx45t_wishbone.vhd=-1
|
log/..\..\test.log=-1
|
|
wishbone\block_test_check/block_check_wb_pkg.vhd=-1
|
wishbone\block_test_check/block_check_wb_pkg.vhd=-1
|
wishbone\block_test_check/block_check_wb_burst_slave.v=-1
|
wishbone\block_test_check/block_check_wb_burst_slave.v=-1
|
wishbone\block_test_check/block_check_wb_config_slave.vhd=-1
|
wishbone\block_test_check/block_check_wb_config_slave.vhd=-1
|
wishbone\block_test_check/cl_test_check.vhd=-1
|
wishbone\block_test_check/cl_test_check.vhd=-1
|
wishbone\block_test_check/block_test_check_wb.vhd=-1
|
wishbone\block_test_check/block_test_check_wb.vhd=-1
|
| Line 566... |
Line 588... |
.\src\testbench\modelsim\required_tests\test0\zz_do\setup_sim.do=Macro
|
.\src\testbench\modelsim\required_tests\test0\zz_do\setup_sim.do=Macro
|
.\src\testbench\ahdl\test_gen.awf=Waveform File
|
.\src\testbench\ahdl\test_gen.awf=Waveform File
|
.\src\testbench\ahdl\pb_wishbone.awf=Waveform File
|
.\src\testbench\ahdl\pb_wishbone.awf=Waveform File
|
.\src\testbench\ahdl\rx.awf=Waveform File
|
.\src\testbench\ahdl\rx.awf=Waveform File
|
.\src\testbench\ahdl\tx.awf=Waveform File
|
.\src\testbench\ahdl\tx.awf=Waveform File
|
|
.\src\testbench\ahdl\run_ahdl.tcl=Tcl Script
|
.\src\top\sp605_lx45t_wishbone.ucf=External File
|
.\src\top\sp605_lx45t_wishbone.ucf=External File
|
.\src\top\sp605_lx45t_wishbone_sopc_wb.vhd=VHDL Source Code
|
.\src\top\sp605_lx45t_wishbone_sopc_wb.vhd=VHDL Source Code
|
.\src\top\sp605_lx45t_wishbone.vhd=VHDL Source Code
|
.\src\top\sp605_lx45t_wishbone.vhd=VHDL Source Code
|
.\test.log=Text File
|
|
.\src\wishbone\block_test_check\block_check_wb_pkg.vhd=VHDL Source Code
|
.\src\wishbone\block_test_check\block_check_wb_pkg.vhd=VHDL Source Code
|
.\src\wishbone\block_test_check\block_check_wb_burst_slave.v=Verilog Source Code
|
.\src\wishbone\block_test_check\block_check_wb_burst_slave.v=Verilog Source Code
|
.\src\wishbone\block_test_check\block_check_wb_config_slave.vhd=VHDL Source Code
|
.\src\wishbone\block_test_check\block_check_wb_config_slave.vhd=VHDL Source Code
|
.\src\wishbone\block_test_check\cl_test_check.vhd=VHDL Source Code
|
.\src\wishbone\block_test_check\cl_test_check.vhd=VHDL Source Code
|
.\src\wishbone\block_test_check\block_test_check_wb.vhd=VHDL Source Code
|
.\src\wishbone\block_test_check\block_test_check_wb.vhd=VHDL Source Code
|
| Line 635... |
Line 657... |
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_intf.sv=SystemVerilog Source Code
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_intf.sv=SystemVerilog Source Code
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_tb_simple_master.sv=SystemVerilog Source Code
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_tb_simple_master.sv=SystemVerilog Source Code
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_tb_simple_ram_slave.v=Verilog Source Code
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_tb_simple_ram_slave.v=Verilog Source Code
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\zz_do\delete.do=Macro
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\zz_do\delete.do=Macro
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\zz_do\setup_sim.do=Macro
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\zz_do\setup_sim.do=Macro
|
|
|
