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[/] [pcie_ds_dma/] [trunk/] [projects/] [sp605_lx45t_wishbone/] [src/] [testbench/] [stend_sp605_wishbone.vhd] - Diff between revs 2 and 10

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-- Title       : stend_sp605_wishbone 
-- Title       : stend_sp605_wishbone 
-- Author      : Dmitry Smekhov
-- Author      : Dmitry Smekhov
-- Company     : Instrumental Systems
-- Company     : Instrumental Systems
-- E-mail      : dsmv@insys.ru
-- E-mail      : dsmv@insys.ru
--
--
-- Version     : 1.0
-- Version     : 1.2
--
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- Description : 
-- Description : Stend for test stend_sp605_wishbone
 
--
 
-------------------------------------------------------------------------------
 
--
 
--  Version 1.2  01.02.2013 Dmitry Smekhov
 
--      Add parameters: test_id, test_log
--
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
--  Version 1.1 (25.10.2011) Kuzmi4
--  Version 1.1 (25.10.2011) Kuzmi4
--      Description: add "assert" for stop simulation after TEST finished.
--      Description: add "assert" for stop simulation after TEST finished.
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use std.textio.all;
use std.textio.all;
use std.textio;
use std.textio;
 
 
entity stend_sp605_wishbone is
entity stend_sp605_wishbone is
 
        generic(
 
                test_id                 : in integer:=0; -- идентификатор теста
 
                test_log                : in string:="src\testbench\log\file_id_"       -- имя файла отчёта
 
        );
end stend_sp605_wishbone;
end stend_sp605_wishbone;
 
 
 
 
architecture stend_sp605_wishbone of stend_sp605_wishbone is
architecture stend_sp605_wishbone of stend_sp605_wishbone is
 
 
--component xilinx_pcie_2_0_rport_v6 is
 
--generic (
 
--          REF_CLK_FREQ   : integer;          -- 0 - 100 MHz, 1 - 125 MHz,  2 - 250 MHz
 
--          ALLOW_X8_GEN2  : boolean;
 
--          PL_FAST_TRAIN  : boolean;
 
--          LINK_CAP_MAX_LINK_SPEED : bit_vector;
 
--          DEVICE_ID : bit_vector;
 
--          LINK_CAP_MAX_LINK_WIDTH  : bit_vector;
 
--          LINK_CAP_MAX_LINK_WIDTH_int  : integer;
 
--          LINK_CTRL2_TARGET_LINK_SPEED  : bit_vector;
 
--          LTSSM_MAX_LINK_WIDTH  : bit_vector;
 
--          DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer;
 
--          USER_CLK_FREQ : integer;
 
--          VC0_TX_LASTPACKET : integer;
 
--          VC0_RX_RAM_LIMIT : bit_vector;
 
--          VC0_TOTAL_CREDITS_PD : integer;
 
--          VC0_TOTAL_CREDITS_CD : integer
 
--);
 
--port  (
 
--
 
--  sys_clk : in std_logic;
 
--  sys_reset_n : in std_logic;
 
--
 
--  pci_exp_rxn : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
 
--  pci_exp_rxp : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
 
--  pci_exp_txn : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
 
--  pci_exp_txp : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0)
 
--
--
--);
--function set_file_name( test_log : in string; test_id: in integer ) return string is
--end component;
--variable      str             : line;
 
--variable      ret             : string( 255 downto 1 );
 
--begin
 
--
 
--      write( str, test_log );
 
--      write( str, string'("_id_") );
 
--      write( str, test_id );
 
--      
 
--      ret:=conv_string( str );
 
--      return ret;
 
--      
 
--      
 
--end set_file_name;
 
 
 
constant        fname_test_log  : string:= test_log & integer'image(test_id) & ".log";
 
 
 
 
signal  clk125                  : std_logic:='0';
signal  clk125                  : std_logic:='0';
signal  clk125p                 : std_logic;
signal  clk125p                 : std_logic;
signal  clk125n                 : std_logic;
signal  clk125n                 : std_logic;
 
 
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variable        data    : std_logic_vector( 31 downto 0 );
variable        data    : std_logic_vector( 31 downto 0 );
variable        str     : LINE;         -- pointer to string
variable        str     : LINE;         -- pointer to string
 
 
begin
begin
 
 
    --test_init( "src\log\test.log" );
        --   test_init( "test.log" );
    test_init( "test.log" );
 
 
    test_init( fname_test_log );
 
 
    wait for 180 us;
    wait for 180 us;
 
 
    --test_dsc_incorrect( cmd, ret );
 
    test_read_4kb( cmd, ret );      -- was original
        case( test_id ) is
    --test_adm_read_8kb( cmd, ret );
                when 0 => test_dsc_incorrect( cmd, ret );
    --test_adm_read_16kb( cmd, ret );
        when 1 => test_read_4kb( cmd, ret );      -- was original
    --test_adm_write_16kb( cmd, ret );
        when 2 => test_adm_read_8kb( cmd, ret );
    --test_block_main( cmd, ret );
        --when 3 => test_adm_read_16kb( cmd, ret );
 
        --when 4 => test_adm_write_16kb( cmd, ret );
 
        --when 5 => test_block_main( cmd, ret );           
 
 
 
                when others => null;
 
        end case;
 
 
    --test_num_1(cmd, ret);
    --test_num_1(cmd, ret);
    --test_num_2(cmd, ret);
    --test_num_2(cmd, ret);
 
 
    --test_wb_1(cmd, ret);
    --test_wb_1(cmd, ret);
    --test_wb_2(cmd, ret);
    --test_wb_2(cmd, ret);
 
 
    test_close;
    test_close;
    --
    --
    -- Print Final Banner
    -- Print Final Banner
    report "Init END OF TEST" severity WARNING;
--    report "Init END OF TEST" severity WARNING;
    assert false
--    assert false
    report "End of TEST; Ending simulation (not a Failure)"
--    report "End of TEST; Ending simulation (not a Failure)"
    severity FAILURE;
--    severity FAILURE;
    wait;
    wait;
 
 
end process pr_main;
end process pr_main;
 
 
end stend_sp605_wishbone;
end stend_sp605_wishbone;

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