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-- Title : stend_sp605_wishbone
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-- Title : stend_sp605_wishbone
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-- Author : Dmitry Smekhov
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-- Author : Dmitry Smekhov
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-- Company : Instrumental Systems
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-- Company : Instrumental Systems
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-- E-mail : dsmv@insys.ru
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-- E-mail : dsmv@insys.ru
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--
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--
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-- Version : 1.0
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-- Version : 1.2
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Description :
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-- Description : Stend for test stend_sp605_wishbone
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.2 01.02.2013 Dmitry Smekhov
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-- Add parameters: test_id, test_log
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Version 1.1 (25.10.2011) Kuzmi4
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-- Version 1.1 (25.10.2011) Kuzmi4
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-- Description: add "assert" for stop simulation after TEST finished.
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-- Description: add "assert" for stop simulation after TEST finished.
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use std.textio.all;
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use std.textio.all;
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use std.textio;
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use std.textio;
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entity stend_sp605_wishbone is
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entity stend_sp605_wishbone is
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generic(
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test_id : in integer:=0; -- идентификатор теста
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test_log : in string:="src\testbench\log\file_id_" -- имя файла отчёта
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);
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end stend_sp605_wishbone;
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end stend_sp605_wishbone;
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architecture stend_sp605_wishbone of stend_sp605_wishbone is
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architecture stend_sp605_wishbone of stend_sp605_wishbone is
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--component xilinx_pcie_2_0_rport_v6 is
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--generic (
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-- REF_CLK_FREQ : integer; -- 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
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-- ALLOW_X8_GEN2 : boolean;
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-- PL_FAST_TRAIN : boolean;
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-- LINK_CAP_MAX_LINK_SPEED : bit_vector;
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-- DEVICE_ID : bit_vector;
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-- LINK_CAP_MAX_LINK_WIDTH : bit_vector;
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-- LINK_CAP_MAX_LINK_WIDTH_int : integer;
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-- LINK_CTRL2_TARGET_LINK_SPEED : bit_vector;
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-- LTSSM_MAX_LINK_WIDTH : bit_vector;
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-- DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer;
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-- USER_CLK_FREQ : integer;
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-- VC0_TX_LASTPACKET : integer;
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-- VC0_RX_RAM_LIMIT : bit_vector;
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-- VC0_TOTAL_CREDITS_PD : integer;
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-- VC0_TOTAL_CREDITS_CD : integer
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--);
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--port (
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--
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-- sys_clk : in std_logic;
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-- sys_reset_n : in std_logic;
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--
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-- pci_exp_rxn : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
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-- pci_exp_rxp : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
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-- pci_exp_txn : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
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-- pci_exp_txp : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0)
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--
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--
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--);
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--function set_file_name( test_log : in string; test_id: in integer ) return string is
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--end component;
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--variable str : line;
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--variable ret : string( 255 downto 1 );
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--begin
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--
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-- write( str, test_log );
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-- write( str, string'("_id_") );
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-- write( str, test_id );
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--
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-- ret:=conv_string( str );
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-- return ret;
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--
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--
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--end set_file_name;
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constant fname_test_log : string:= test_log & integer'image(test_id) & ".log";
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signal clk125 : std_logic:='0';
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signal clk125 : std_logic:='0';
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signal clk125p : std_logic;
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signal clk125p : std_logic;
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signal clk125n : std_logic;
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signal clk125n : std_logic;
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variable data : std_logic_vector( 31 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
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variable str : LINE; -- pointer to string
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variable str : LINE; -- pointer to string
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begin
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begin
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--test_init( "src\log\test.log" );
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-- test_init( "test.log" );
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test_init( "test.log" );
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test_init( fname_test_log );
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wait for 180 us;
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wait for 180 us;
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--test_dsc_incorrect( cmd, ret );
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test_read_4kb( cmd, ret ); -- was original
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case( test_id ) is
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--test_adm_read_8kb( cmd, ret );
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when 0 => test_dsc_incorrect( cmd, ret );
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--test_adm_read_16kb( cmd, ret );
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when 1 => test_read_4kb( cmd, ret ); -- was original
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--test_adm_write_16kb( cmd, ret );
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when 2 => test_adm_read_8kb( cmd, ret );
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--test_block_main( cmd, ret );
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--when 3 => test_adm_read_16kb( cmd, ret );
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--when 4 => test_adm_write_16kb( cmd, ret );
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--when 5 => test_block_main( cmd, ret );
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when others => null;
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end case;
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--test_num_1(cmd, ret);
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--test_num_1(cmd, ret);
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--test_num_2(cmd, ret);
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--test_num_2(cmd, ret);
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--test_wb_1(cmd, ret);
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--test_wb_1(cmd, ret);
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--test_wb_2(cmd, ret);
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--test_wb_2(cmd, ret);
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test_close;
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test_close;
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--
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--
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-- Print Final Banner
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-- Print Final Banner
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report "Init END OF TEST" severity WARNING;
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-- report "Init END OF TEST" severity WARNING;
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assert false
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-- assert false
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report "End of TEST; Ending simulation (not a Failure)"
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-- report "End of TEST; Ending simulation (not a Failure)"
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severity FAILURE;
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-- severity FAILURE;
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wait;
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wait;
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end process pr_main;
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end process pr_main;
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end stend_sp605_wishbone;
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end stend_sp605_wishbone;
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