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URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [soft/] [linux/] [application/] [wb_test/] [src/] [work/] [wb_teststrm.cpp] - Diff between revs 2 and 19

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Rev 2 Rev 19
Line 62... Line 62...
 
 
void WB_TestStrm::Prepare( void )
void WB_TestStrm::Prepare( void )
{
{
 
 
 
 
    PrepareAdm();
    PrepareWb();
 
 
    rd0.trd=trdNo;
    rd0.trd=trdNo;
    rd0.Strm=strmNo;
    rd0.Strm=strmNo;
    pBrd->StreamInit( rd0.Strm, CntBuffer, SizeBuferOfBytes, rd0.trd, 1, isCycle, isSystem, isAgreeMode );
   // pBrd->StreamInit( rd0.Strm, CntBuffer, SizeBuferOfBytes, rd0.trd, 1, isCycle, isSystem, isAgreeMode );
 
 
    bufIsvi = new U32[SizeBlockOfWords*2];
    bufIsvi = new U32[SizeBlockOfWords*2];
    //pBrd->StreamInit( strm, CntBuffer, SizeBuferOfBytes, rd0.trd, 1, 0, 0 );
    pBrd->StreamInit( rd0.Strm, CntBuffer, SizeBuferOfBytes, U32(0x3000),U32(1), 0, 1, U32(0) );
}
}
 
 
void WB_TestStrm::Start( void )
void WB_TestStrm::Start( void )
{
{
    int res = pthread_attr_init(&attrThread_);
    int res = pthread_attr_init(&attrThread_);
Line 133... Line 133...
    //BRDC_fprintf( stderr, "%10s %10d %10d %10d %10d\n", "PACKAGE :", pkg_out.BlockWr, pkg_in.BlockRd, pkg_in.BlockOk, pkg_in.BlockError );
    //BRDC_fprintf( stderr, "%10s %10d %10d %10d %10d\n", "PACKAGE :", pkg_out.BlockWr, pkg_in.BlockRd, pkg_in.BlockOk, pkg_in.BlockError );
    //BRDC_fprintf( stderr, "%10s %10d %10d %10d %10d\n", "FIFO_0 :", tr0.BlockWr, rd0.BlockRd, rd0.BlockOk, rd0.BlockError );
    //BRDC_fprintf( stderr, "%10s %10d %10d %10d %10d\n", "FIFO_0 :", tr0.BlockWr, rd0.BlockRd, rd0.BlockOk, rd0.BlockError );
    //BRDC_fprintf( stderr, "%10s %10d %10d %10d %10d\n", "FIFO_1 :", tr1.BlockWr, rd1.BlockRd, rd1.BlockOk, rd1.BlockError );
    //BRDC_fprintf( stderr, "%10s %10d %10d %10d %10d\n", "FIFO_1 :", tr1.BlockWr, rd1.BlockRd, rd1.BlockOk, rd1.BlockError );
 
 
    U32 status = 0; //pBrd->RegPeekDir( rd0.trd, 0 ) & 0xFFFF;
    U32 status = 0; //pBrd->RegPeekDir( rd0.trd, 0 ) & 0xFFFF;
    BRDC_fprintf( stderr, "%6s %3d %10d %10d %10d %10d  %9.1f %10.1f     0x%.4X  %d %4d %4f\r", "TRD :", rd0.trd, rd0.BlockWr, rd0.BlockRd, rd0.BlockOk, rd0.BlockError, rd0.VelocityCurrent, rd0.VelocityAvarage, status, IsviStatus, IsviCnt, rd0.fftTime_us );
    rd0.BlockWr=pBrd->wb_block_read( 1, 0x11 );
 
 
 
    BRDC_fprintf( stdout, "%6s %3d %10d %10d %10d %10d  %9.1f %10.1f     0x%.4X  %d %4d %4f\r", "TRD :", rd0.trd, rd0.BlockWr, rd0.BlockRd, rd0.BlockOk, rd0.BlockError, rd0.VelocityCurrent, rd0.VelocityAvarage, status, IsviStatus, IsviCnt, rd0.fftTime_us );
 
 
 
 
 
 
 
 
}
}
Line 287... Line 289...
    if( isAdmReg2 )
    if( isAdmReg2 )
        PrepareAdmReg( fnameAdmReg2 );
        PrepareAdmReg( fnameAdmReg2 );
 
 
    pBrd->RegPokeInd( 4, 0, 0x2038 );
    pBrd->RegPokeInd( 4, 0, 0x2038 );
*/
*/
 
    pBrd->StreamStart( rd0.Strm );
 
 
 
    U32 val;
 
    val=pBrd->wb_block_read( 1, 0 );
 
    BRDC_fprintf( stderr, "ID=0x%.4X \n", val );
 
 
 
    val=pBrd->wb_block_read( 1, 1 );
 
    BRDC_fprintf( stderr, "VER=0x%.4X \n", val );
 
 
 
    val=pBrd->wb_block_read( 1, 8 );
 
    BRDC_fprintf( stderr, "GEN_CTRL=0x%.4X \n", val );
 
 
 
    pBrd->wb_block_write( 1, 9, 5 );
 
    pBrd->wb_block_write( 1, 8, 0x6A0 );
 
 
 
    val=pBrd->wb_block_read( 1, 8 );
 
    BRDC_fprintf( stderr, "GEN_CTRL=0x%.4X \n", val );
 
 
    rd0.time_last=rd0.time_start=0 ;//GetTickCount();
    rd0.time_last=rd0.time_start=0 ;//GetTickCount();
 
 
 
 
    for( ; ; )
    for( ; ; )
    {
    {
Line 332... Line 352...
    //return;
    //return;
 
 
    for( kk=0; kk<16; kk++ )
    for( kk=0; kk<16; kk++ )
    {
    {
        ret=pBrd->StreamGetBuf( pr->Strm, &ptr );
        ret=pBrd->StreamGetBuf( pr->Strm, &ptr );
 
        //ret=0;
        if( ret )
        if( ret )
        { // Проверка буфера стрима
        { // Проверка буфера стрима
 
 
                for( unsigned ii=0; ii<CntBlockInBuffer; ii++ )
                for( unsigned ii=0; ii<CntBlockInBuffer; ii++ )
                {
                {
Line 393... Line 414...
*/
*/
 
 
}
}
 
 
 
 
void WB_TestStrm::PrepareAdm( void )
void WB_TestStrm::PrepareWb( void )
{
{
/*
 
    U32 trd=trdNo;
 
    U32 id, id_mod, ver;
 
    BRDC_fprintf( stderr, "\nПодготовка тетрады\n" );
 
 
 
 
 
    id = pBrd->RegPeekInd( trd, 0x100 );
 
    id_mod = pBrd->RegPeekInd( trd, 0x101 );
 
    ver = pBrd->RegPeekInd( trd, 0x102 );
 
 
 
    //pBrd->RegPokeInd( trd, 0, 0x2038 );
 
 
 
    BRDC_fprintf( stderr, "\nТетрада %d  ID: 0x%.2X MOD: %d  VER: %d.%d \n\n",
    BRDC_fprintf( stderr, "\nPrepare TEST_GENERATE\n" );
            trd, id, id_mod, (ver>>8) & 0xFF, ver&0xFF );
 
 
 
 
 
    //if( fnameDDS )
 
    //  PrepareDDS();
 
 
 
 
    BlockMode = DataType <<8;
 
    BlockMode |= DataFix <<7;
 
 
    if( isMainTest )
    //if( isTestCtrl )
        PrepareMain();
    {
 
        pBrd->wb_block_write( 1, 9, 1 );
 
        pBrd->wb_block_write( 1, 9, BlockMode );
    BlockMode = DataType <<8;
    }
    BlockMode |= DataFix <<7;
 
 
 
    if( isTestCtrl )
 
        PrepareTestCtrl();
 
 
 
    if( isAdmReg )
 
        PrepareAdmReg( fnameAdmReg );
 
 
 
 
 
    IsviStatus=0;
    IsviStatus=0;
    IsviCnt=0;
    IsviCnt=0;
    isIsvi=0;
    isIsvi=0;
    if( fnameIsvi )
    if( fnameIsvi )
    {
    {
        IsviStatus=1;
        IsviStatus=1;
        isIsvi=1;
        isIsvi=1;
    }
    }
 
 
*/
 
}
}
 
 
 
 
 
 
 
 

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