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#ifndef _CTRL_STRM_H_
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#ifndef _CTRL_STRM_H_
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#include "ctrlstrm.h"
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#include "ctrlstrm.h"
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#endif
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#endif
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#ifdef __VERBOSE__
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#include <stdio.h>
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#define DEBUG_PRINT(fmt, args...) fprintf(stderr, fmt, ## args)
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#else
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#define DEBUG_PRINT(fmt, args...)
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#endif
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class board {
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class board {
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private:
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private:
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virtual int core_open(const char *name) = 0;
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virtual int core_open(const char *name) = 0;
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virtual int core_load_dsp() = 0;
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virtual int core_load_dsp() = 0;
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virtual int core_load_pld() = 0;
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virtual int core_load_pld() = 0;
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virtual int core_board_info() = 0;
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virtual int core_board_info() = 0;
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virtual int core_pld_info() = 0;
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virtual int core_pld_info() = 0;
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virtual int core_resource() = 0;
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virtual int core_resource() = 0;
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virtual void core_delay(int ms) = 0;
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virtual u32 core_alloc(int DmaChan, BRDctrl_StreamCBufAlloc* sSCA) = 0;
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virtual u32 core_alloc(int DmaChan, BRDctrl_StreamCBufAlloc* sSCA) = 0;
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virtual u32 core_allocate_memory(int DmaChan, void** pBuf, u32 blkSize, u32 blkNum, u32 isSysMem, u32 dir, u32 addr) = 0;
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virtual u32 core_allocate_memory(int DmaChan, void** pBuf, u32 blkSize,
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u32 blkNum, u32 isSysMem, u32 dir,
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u32 addr, BRDstrm_Stub **pStub ) = 0;
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virtual u32 core_free_memory(int DmaChan) = 0;
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virtual u32 core_free_memory(int DmaChan) = 0;
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virtual u32 core_start_dma(int DmaChan, int IsCycling) = 0;
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virtual u32 core_start_dma(int DmaChan, int IsCycling) = 0;
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virtual u32 core_stop_dma(int DmaChan) = 0;
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virtual u32 core_stop_dma(int DmaChan) = 0;
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virtual u32 core_state_dma(int DmaChan, u32 msTimeout, int& state, u32& blkNum) = 0;
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virtual u32 core_state_dma(int DmaChan, u32 msTimeout, int& state, u32& blkNum) = 0;
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virtual u32 core_wait_buffer(int DmaChan, u32 msTimeout) = 0;
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virtual u32 core_wait_buffer(int DmaChan, u32 msTimeout) = 0;
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int brd_init();
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int brd_init();
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int brd_reset();
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int brd_reset();
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int brd_close();
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int brd_close();
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int brd_load_dsp();
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int brd_load_dsp();
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int brd_load_pld();
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int brd_load_pld();
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void brd_delay(int ms);
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int brd_board_info();
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int brd_board_info();
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int brd_pld_info();
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int brd_pld_info();
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int brd_resource();
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int brd_resource();
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//! Методы управления каналами DMA BRDSHELL
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//! Методы управления каналами DMA BRDSHELL
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u32 dma_alloc(int DmaChan, BRDctrl_StreamCBufAlloc* sSCA);
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u32 dma_alloc(int DmaChan, BRDctrl_StreamCBufAlloc* sSCA);
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u32 dma_allocate_memory(int DmaChan, void** pBuf, u32 blkSize, u32 blkNum, u32 isSysMem, u32 dir, u32 addr);
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u32 dma_allocate_memory(int DmaChan, void** pBuf, u32 blkSize,
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u32 blkNum, u32 isSysMem,
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u32 dir, u32 addr, BRDstrm_Stub **pStub);
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u32 dma_free_memory(int DmaChan);
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u32 dma_free_memory(int DmaChan);
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u32 dma_start(int DmaChan, int IsCycling);
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u32 dma_start(int DmaChan, int IsCycling);
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u32 dma_stop(int DmaChan);
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u32 dma_stop(int DmaChan);
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u32 dma_state(int DmaChan, u32 msTimeout, int& state, u32& blkNum);
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u32 dma_state(int DmaChan, u32 msTimeout, int& state, u32& blkNum);
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u32 dma_wait_buffer(int DmaChan, u32 msTimeout);
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u32 dma_wait_buffer(int DmaChan, u32 msTimeout);
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void brd_bar0_write( u32 offset, u32 val );
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void brd_bar0_write( u32 offset, u32 val );
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u32 brd_bar1_read( u32 offset );
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u32 brd_bar1_read( u32 offset );
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void brd_bar1_write( u32 offset, u32 val );
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void brd_bar1_write( u32 offset, u32 val );
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};
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};
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//#define RegPeekDir(trd, reg) brd_reg_peek_dir((trd), (reg))
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//! Тип конструктора объектов
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//#define RegPeekInd(trd, reg) brd_reg_peek_ind((trd), (reg));
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typedef board* (*board_factory)(void);
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//#define RegPokeDir(trd, reg, val) brd_reg_poke_dir((trd), (reg), (val));
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//#define RegPokeOnd(trd, reg, val) brd_reg_poke_ind((trd), (reg), (val));
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#endif //__BOARD_H__
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#endif //__BOARD_H__
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