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#ifndef __PEX_BOARD_H__
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#ifndef __PEX_BOARD_H__
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#include "pex_board.h"
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#include "pex_board.h"
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#endif
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#endif
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#ifndef __DMA_MEMORY__H__
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#include "dma_memory.h"
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#endif
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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#include <stdio.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdlib.h>
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pex_board::pex_board()
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pex_board::pex_board()
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{
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{
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fd = -1;
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fd = -1;
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bar0 = bar1 = NULL;
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bar0 = bar1 = NULL;
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memset(&bi, 0, sizeof(bi));
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memset(&bi, 0, sizeof(bi));
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m_dma = new dma_memory();
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//m_dma = new dma_memory();
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}
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}
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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pex_board::~pex_board()
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pex_board::~pex_board()
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{
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{
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if(m_dma) delete m_dma;
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//if(m_dma) delete m_dma;
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core_close();
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core_close();
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}
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}
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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}
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}
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// подготовим к работе ПЛИС ADM
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// подготовим к работе ПЛИС ADM
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fprintf(stderr,"%s(): Prepare ADM PLD.\n", __FUNCTION__);
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fprintf(stderr,"%s(): Prepare ADM PLD.\n", __FUNCTION__);
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core_block_write( 0, 8, 0);
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core_block_write( 0, 8, 0);
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core_pause(100); // pause ~ 100 msec
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core_delay(100); // pause ~ 100 msec
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for(i = 0; i < 10; i++)
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for(i = 0; i < 10; i++)
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{
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{
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core_block_write( 0, 8, 1);
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core_block_write( 0, 8, 1);
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core_pause(100); // pause ~ 100 msec
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core_delay(100); // pause ~ 100 msec
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core_block_write( 0, 8, 3);
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core_block_write( 0, 8, 3);
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core_pause(100); // pause ~ 100 msec
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core_delay(100); // pause ~ 100 msec
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core_block_write( 0, 8, 7);
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core_block_write( 0, 8, 7);
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core_pause(100); // pause ~ 100 msec
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core_delay(100); // pause ~ 100 msec
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temp = core_block_read( 0, 010 ) & 0x01;
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temp = core_block_read( 0, 010 ) & 0x01;
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if(temp)
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if(temp)
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break;
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break;
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}
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}
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core_block_write( 0, 8, 0xF );
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core_block_write( 0, 8, 0xF );
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core_pause(100); // pause ~ 100 msec
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core_delay(100); // pause ~ 100 msec
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return 0;
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return 0;
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}
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}
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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case 0x70: str="AMBPEX5_SDRAM "; break;
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case 0x70: str="AMBPEX5_SDRAM "; break;
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case 0x71: str="TRD_MSG "; break;
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case 0x71: str="TRD_MSG "; break;
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case 0x72: str="TRD_TS201 "; break;
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case 0x72: str="TRD_TS201 "; break;
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case 0x73: str="TRD_STREAM_IN "; break;
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case 0x73: str="TRD_STREAM_IN "; break;
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case 0x74: str="TRD_STREAM_OUT"; break;
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case 0x74: str="TRD_STREAM_OUT"; break;
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case 0xA0: str="TRD_ADC "; break;
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case 0xA1: str="TRD_DAC "; break;
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case 0x91: str="TRD_EMAC "; break;
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default: str="UNKNOWN"; break;
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default: str="UNKNOWN"; break;
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}
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}
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fprintf(stderr, " %d 0x%.4X %s ", ii, d, str );
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fprintf(stderr, " %d 0x%.4X %s ", ii, d, str );
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return 0;
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return 0;
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}
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}
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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void pex_board::core_pause(int ms)
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void pex_board::core_delay(int ms)
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{
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{
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struct timeval tv = {0, 0};
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struct timeval tv = {0, 0};
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tv.tv_usec = 1000*ms;
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tv.tv_usec = 1000*ms;
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select(0,NULL,NULL,NULL,&tv);
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select(0,NULL,NULL,NULL,&tv);
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status = bar1[Status/4];
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status = bar1[Status/4];
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if( status & 1 )
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if( status & 1 )
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break;
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break;
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if( ii>10000 )
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if( ii>10000 )
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core_pause( 1 );
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core_delay( 1 );
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if( ii>20000 ) {
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if( ii>20000 ) {
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return 0xFFFF;
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return 0xFFFF;
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}
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}
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}
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}
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status = bar1[Status/4];
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status = bar1[Status/4];
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if( status & 1 )
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if( status & 1 )
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break;
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break;
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if( ii>10000 )
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if( ii>10000 )
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core_pause( 1 );
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core_delay( 1 );
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if( ii>20000 ) {
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if( ii>20000 ) {
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return;
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return;
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}
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}
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}
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}
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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u32 pex_board::core_bar0_read( u32 offset )
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u32 pex_board::core_bar0_read( u32 offset )
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{
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{
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return bar0[offset];
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return bar0[2*offset];
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}
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}
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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void pex_board::core_bar0_write( u32 offset, u32 val )
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void pex_board::core_bar0_write( u32 offset, u32 val )
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{
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{
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bar0[offset] = val;
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bar0[2*offset] = val;
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}
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}
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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u32 pex_board::core_bar1_read( u32 offset )
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u32 pex_board::core_bar1_read( u32 offset )
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{
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{
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return bar1[offset];
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return bar1[2*offset];
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}
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}
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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void pex_board::core_bar1_write( u32 offset, u32 val )
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void pex_board::core_bar1_write( u32 offset, u32 val )
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return 0;
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return 0;
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}
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}
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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u32 pex_board::core_allocate_memory(int DmaChan, void** pBuf, u32 blkSize, u32 blkNum, u32 isSysMem, u32 dir, u32 addr)
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u32 pex_board::core_allocate_memory(int DmaChan,
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void** pBuf,
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u32 blkSize,
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u32 blkNum,
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u32 isSysMem,
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u32 dir,
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u32 addr,
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BRDstrm_Stub **pStub )
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{
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{
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m_DescrSize[DmaChan] = sizeof(AMB_MEM_DMA_CHANNEL) + (blkNum - 1) * sizeof(void*);
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m_DescrSize[DmaChan] = sizeof(AMB_MEM_DMA_CHANNEL) + (blkNum - 1) * sizeof(void*);
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m_Descr[DmaChan] = (AMB_MEM_DMA_CHANNEL*) new u8[m_DescrSize[DmaChan]];
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m_Descr[DmaChan] = (AMB_MEM_DMA_CHANNEL*) new u8[m_DescrSize[DmaChan]];
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m_Descr[DmaChan]->DmaChanNum = DmaChan;
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m_Descr[DmaChan]->DmaChanNum = DmaChan;
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Line 649... |
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m_Descr[DmaChan]->pStub = StubAddress;
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m_Descr[DmaChan]->pStub = StubAddress;
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}
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}
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*pBuf = &m_Descr[DmaChan]->pBlock[0];
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*pBuf = &m_Descr[DmaChan]->pBlock[0];
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*pStub = (BRDstrm_Stub*)m_Descr[DmaChan]->pStub;
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return 0;
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return 0;
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}
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}
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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