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[/] [pcie_sg_dma/] [trunk/] [rtl/] [FIFO_Wrapper.vhd] - Diff between revs 2 and 3
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-- Company: ziti, Uni. HD
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-- Company: ziti, Uni. HD
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-- Engineer: wgao
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-- Engineer: wgao
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--
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--
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-- Create Date: 16:37:22 12 Feb 2009
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-- Create Date: 16:37:22 12 Feb 2009
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-- Design Name:
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-- Design Name:
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-- Module Name: eb_wrapper - Behavioral
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-- Module Name: FIFO_wrapper - Behavioral
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-- Project Name:
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-- Project Name:
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-- Target Devices:
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-- Target Devices:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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--
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--
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity eb_wrapper is
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entity FIFO_wrapper is
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Generic (
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Generic (
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C_ASYNFIFO_WIDTH : integer := 72
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C_ASYNFIFO_WIDTH : integer := 72
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);
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);
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Port (
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Port (
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wr_clk : IN std_logic;
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wr_clk : IN std_logic;
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empty : OUT std_logic;
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empty : OUT std_logic;
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data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
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data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
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rst : IN std_logic
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rst : IN std_logic
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);
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);
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end entity eb_wrapper;
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end entity FIFO_wrapper;
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architecture Behavioral of eb_wrapper is
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architecture Behavioral of FIFO_wrapper is
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--- 16384 x 72
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--- 16384 x 72
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component eb_fifo
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component eb_fifo
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port (
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port (
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wr_clk : IN std_logic;
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wr_clk : IN std_logic;
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