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[/] [pcie_sg_dma/] [trunk/] [rtl/] [tlpControl.vhd] - Diff between revs 2 and 3

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Rev 2 Rev 3
Line 37... Line 37... 
 
 
 
 
      --  Test pin, emulating DDR data flow discontinuity
 
      --  Test pin, emulating DDR data flow discontinuity
 
      mbuf_UserFull            : IN   std_logic;
 
      mbuf_UserFull            : IN   std_logic;
 
      trn_Blinker              : OUT  std_logic;
 
      trn_Blinker              : OUT  std_logic;
 
 
 
 
 
      -- DCB protocol interface
 
--      -- DCB protocol interface
 
      protocol_link_act        : IN  std_logic_vector(2-1 downto 0);
 
--      protocol_link_act        : IN  std_logic_vector(2-1 downto 0);
 
      protocol_rst             : OUT std_logic;
 
--      protocol_rst             : OUT std_logic;
 
 
 
--
 
      -- Interrupter triggers
 
--      -- Interrupter triggers
 
      DAQ_irq                  : IN  std_logic;
 
--      DAQ_irq                  : IN  std_logic;
 
      CTL_irq                  : IN  std_logic;
 
--      CTL_irq                  : IN  std_logic;
 
      DLM_irq                  : IN  std_logic;
 
--      DLM_irq                  : IN  std_logic;
 
 
 
--
 
      -- Fabric side: CTL Rx
 
--      -- Fabric side: CTL Rx
 
      ctl_rv                   : OUT std_logic;
 
--      ctl_rv                   : OUT std_logic;
 
      ctl_rd                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
--      ctl_rd                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
 
 
--
 
      -- Fabric side: CTL Tx
 
--      -- Fabric side: CTL Tx
 
      ctl_ttake                : OUT std_logic;
 
--      ctl_ttake                : OUT std_logic;
 
      ctl_tv                   : IN  std_logic;
 
--      ctl_tv                   : IN  std_logic;
 
      ctl_td                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
--      ctl_td                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
      ctl_tstop                : OUT std_logic;
 
--      ctl_tstop                : OUT std_logic;
 
 
 
--
 
      ctl_reset                : OUT std_logic;
 
--      ctl_reset                : OUT std_logic;
 
      ctl_status               : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
--      ctl_status               : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
 
 
--
 
      -- Fabric side: DLM Rx
 
--      -- Fabric side: DLM Rx
 
      dlm_tv                   : OUT std_logic;
 
--      dlm_tv                   : OUT std_logic;
 
      dlm_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
--      dlm_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
 
 
--
 
      -- Fabric side: DLM Tx
 
--      -- Fabric side: DLM Tx
 
      dlm_rv                   : IN  std_logic;
 
--      dlm_rv                   : IN  std_logic;
 
      dlm_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
--      dlm_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
 
 
 
 
      -- Event Buffer FIFO interface
 
      -- Event Buffer FIFO interface
 
      eb_FIFO_we               : OUT std_logic;
 
      eb_FIFO_we               : OUT std_logic;
 
      eb_FIFO_wsof             : OUT std_logic;
 
      eb_FIFO_wsof             : OUT std_logic;
 
      eb_FIFO_weof             : OUT std_logic;
 
      eb_FIFO_weof             : OUT std_logic;
Line 126... Line 126... 
      -- DDR payload FIFO Read Port
 
      -- DDR payload FIFO Read Port
 
      DDR_FIFO_RdEn            : OUT std_logic;
 
      DDR_FIFO_RdEn            : OUT std_logic;
 
      DDR_FIFO_Empty           : IN  std_logic;
 
      DDR_FIFO_Empty           : IN  std_logic;
 
      DDR_FIFO_RdQout          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
      DDR_FIFO_RdQout          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
 
 
 
 
      -- Data generator table write
 
--      -- Data generator table write
 
      tab_we                   : OUT std_logic_vector(2-1 downto 0);
 
--      tab_we                   : OUT std_logic_vector(2-1 downto 0);
 
      tab_wa                   : OUT std_logic_vector(12-1 downto 0);
 
--      tab_wa                   : OUT std_logic_vector(12-1 downto 0);
 
      tab_wd                   : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
--      tab_wd                   : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
 
 
--
 
      DG_is_Running            : IN  std_logic;
 
--      DG_is_Running            : IN  std_logic;
 
      DG_Reset                 : OUT std_logic;
 
--      DG_Reset                 : OUT std_logic;
 
      DG_Mask                  : OUT std_logic;
 
--      DG_Mask                  : OUT std_logic;
 
 
 
 
 
      -- Common interface
 
      -- Common interface
 
      trn_clk                  : IN  std_logic;
 
      trn_clk                  : IN  std_logic;
 
      trn_reset_n              : IN  std_logic;
 
      trn_reset_n              : IN  std_logic;
 
      trn_lnk_up_n             : IN  std_logic;
 
      trn_lnk_up_n             : IN  std_logic;
Line 369... Line 369... 
 
 
 
 
      DDR_wr_full        : IN    std_logic;
 
      DDR_wr_full        : IN    std_logic;
 
 
 
 
 
      Link_Buf_full      : IN  std_logic;
 
      Link_Buf_full      : IN  std_logic;
 
 
 
 
 
      -- Data generator table write
 
--      -- Data generator table write
 
      tab_we             : OUT std_logic_vector(2-1 downto 0);
 
--      tab_we             : OUT std_logic_vector(2-1 downto 0);
 
      tab_wa             : OUT std_logic_vector(12-1 downto 0);
 
--      tab_wa             : OUT std_logic_vector(12-1 downto 0);
 
      tab_wd             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
--      tab_wd             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
 
 
 
 
      -- Interrupt generator signals
 
      -- Interrupt generator signals
 
      IG_Reset           : IN  std_logic;
 
      IG_Reset           : IN  std_logic;
 
      IG_Host_Clear      : IN  std_logic;
 
      IG_Host_Clear      : IN  std_logic;
 
      IG_Latency         : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
 
      IG_Latency         : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
Line 499... Line 499... 
  -- United memory space consisting of registers.
 
  -- United memory space consisting of registers.
 
  --
 
  --
 
  component Regs_Group
 
  component Regs_Group
 
    port (
 
    port (
 
 
 
 
 
      -- DCB protocol interface
 
--      -- DCB protocol interface
 
                protocol_link_act        : IN  std_logic_vector(2-1 downto 0);
 
--              protocol_link_act        : IN  std_logic_vector(2-1 downto 0);
 
                protocol_rst             : OUT std_logic;
 
--              protocol_rst             : OUT std_logic;
 
 
 
--
 
      -- Fabric side: CTL Rx
 
--      -- Fabric side: CTL Rx
 
      ctl_rv                   : OUT std_logic;
 
--      ctl_rv                   : OUT std_logic;
 
      ctl_rd                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
--      ctl_rd                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
 
 
--
 
      -- Fabric side: CTL Tx
 
--      -- Fabric side: CTL Tx
 
      ctl_ttake                : OUT std_logic;
 
--      ctl_ttake                : OUT std_logic;
 
      ctl_tv                   : IN  std_logic;
 
--      ctl_tv                   : IN  std_logic;
 
      ctl_td                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
--      ctl_td                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
      ctl_tstop                : OUT std_logic;
 
--      ctl_tstop                : OUT std_logic;
 
 
 
--
 
      ctl_reset                : OUT std_logic;
 
--      ctl_reset                : OUT std_logic;
 
      ctl_status               : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
--      ctl_status               : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
 
 
--
 
      -- Fabric side: DLM Rx
 
--      -- Fabric side: DLM Rx
 
      dlm_tv                   : OUT std_logic;
 
--      dlm_tv                   : OUT std_logic;
 
      dlm_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
--      dlm_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
 
 
--
 
      -- Fabric side: DLM Tx
 
--      -- Fabric side: DLM Tx
 
      dlm_rv                   : IN  std_logic;
 
--      dlm_rv                   : IN  std_logic;
 
      dlm_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
--      dlm_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
 
 
 
 
      -- Event Buffer status
 
      -- Event Buffer status
 
      eb_FIFO_Status           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
      eb_FIFO_Status           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
      eb_FIFO_Rst              : OUT std_logic;
 
      eb_FIFO_Rst              : OUT std_logic;
 
 
 
 
Line 614... Line 614... 
      MRd_Channel_Rst          : OUT std_logic;
 
      MRd_Channel_Rst          : OUT std_logic;
 
      Tx_Reset                 : OUT std_logic;
 
      Tx_Reset                 : OUT std_logic;
 
 
 
 
 
      -- to Interrupt module
 
      -- to Interrupt module
 
      Sys_IRQ                  : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
      Sys_IRQ                  : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
      DAQ_irq                  : IN  std_logic;
 
--      DAQ_irq                  : IN  std_logic;
 
      CTL_irq                  : IN  std_logic;
 
--      CTL_irq                  : IN  std_logic;
 
      DLM_irq                  : IN  std_logic;
 
--      DLM_irq                  : IN  std_logic;
 
 
 
 
 
      -- System error and info
 
      -- System error and info
 
      eb_FIFO_ow               : IN  std_logic;
 
      eb_FIFO_ow               : IN  std_logic;
 
      Tx_TimeOut               : IN  std_logic;
 
      Tx_TimeOut               : IN  std_logic;
 
      Tx_eb_TimeOut            : IN  std_logic;
 
      Tx_eb_TimeOut            : IN  std_logic;
Line 634... Line 634... 
      IG_Latency               : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
 
      IG_Latency               : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
 
      IG_Num_Assert            : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
 
      IG_Num_Assert            : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
 
      IG_Num_Deassert          : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
 
      IG_Num_Deassert          : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
 
      IG_Asserting             : IN  std_logic;
 
      IG_Asserting             : IN  std_logic;
 
 
 
 
 
      -- Data generator control
 
--      -- Data generator control
 
      DG_is_Running            : IN  std_logic;
 
--      DG_is_Running            : IN  std_logic;
 
      DG_Reset                 : OUT std_logic;
 
--      DG_Reset                 : OUT std_logic;
 
      DG_Mask                  : OUT std_logic;
 
--      DG_Mask                  : OUT std_logic;
 
 
 
 
 
      -- Common interface
 
      -- Common interface
 
      trn_clk                  : IN  std_logic;
 
      trn_clk                  : IN  std_logic;
 
      trn_lnk_up_n             : IN  std_logic;
 
      trn_lnk_up_n             : IN  std_logic;
 
      trn_reset_n              : IN  std_logic
 
      trn_reset_n              : IN  std_logic
Line 1160... Line 1160... 
 
 
 
 
 
 
 
 
      Link_Buf_full       =>  Link_Buf_full   , -- IN    std_logic;
 
      Link_Buf_full       =>  Link_Buf_full   , -- IN    std_logic;
 
 
 
 
 
 
 
 
 
      -- Data generator table write
 
--      -- Data generator table write
 
      tab_we              =>  tab_we          , -- OUT std_logic_vector(2-1 downto 0);
 
--      tab_we              =>  tab_we          , -- OUT std_logic_vector(2-1 downto 0);
 
      tab_wa              =>  tab_wa          , -- OUT std_logic_vector(12-1 downto 0);
 
--      tab_wa              =>  tab_wa          , -- OUT std_logic_vector(12-1 downto 0);
 
      tab_wd              =>  tab_wd          , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
--      tab_wd              =>  tab_wd          , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
 
 
 
 
      -- Additional
 
      -- Additional
 
      cfg_dcommand        =>  cfg_dcommand         ,  -- IN  std_logic_vector(15 downto 0)
 
      cfg_dcommand        =>  cfg_dcommand         ,  -- IN  std_logic_vector(15 downto 0)
 
      localID             =>  localID                 -- IN  std_logic_vector(15 downto 0)
 
      localID             =>  localID                 -- IN  std_logic_vector(15 downto 0)
 
    );
 
    );
Line 1271... Line 1271... 
  -- ------------------------------------------------
 
  -- ------------------------------------------------
 
   Memory_Space:
 
   Memory_Space:
 
   Regs_Group
 
   Regs_Group
 
   PORT MAP(
 
   PORT MAP(
 
 
 
 
 
      -- DCB protocol interface
 
--      -- DCB protocol interface
 
      protocol_link_act   =>  protocol_link_act    ,  -- IN  std_logic_vector(2-1 downto 0);
 
--      protocol_link_act   =>  protocol_link_act    ,  -- IN  std_logic_vector(2-1 downto 0);
 
      protocol_rst        =>  protocol_rst         ,  -- OUT std_logic;
 
--      protocol_rst        =>  protocol_rst         ,  -- OUT std_logic;
 
 
 
--
 
      -- Fabric side: CTL Rx
 
--      -- Fabric side: CTL Rx
 
      ctl_rv              =>  ctl_rv               ,  -- OUT std_logic;
 
--      ctl_rv              =>  ctl_rv               ,  -- OUT std_logic;
 
      ctl_rd              =>  ctl_rd               ,  -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
--      ctl_rd              =>  ctl_rd               ,  -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
 
 
--
 
      -- Fabric side: CTL Tx
 
--      -- Fabric side: CTL Tx
 
      ctl_ttake           =>  ctl_ttake            ,  -- OUT std_logic;
 
--      ctl_ttake           =>  ctl_ttake            ,  -- OUT std_logic;
 
      ctl_tv              =>  ctl_tv               ,  -- IN  std_logic;
 
--      ctl_tv              =>  ctl_tv               ,  -- IN  std_logic;
 
      ctl_td              =>  ctl_td               ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
--      ctl_td              =>  ctl_td               ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
      ctl_tstop           =>  ctl_tstop            ,  -- OUT std_logic;
 
--      ctl_tstop           =>  ctl_tstop            ,  -- OUT std_logic;
 
 
 
--
 
      ctl_reset           =>  ctl_reset            ,  -- OUT std_logic;
 
--      ctl_reset           =>  ctl_reset            ,  -- OUT std_logic;
 
      ctl_status          =>  ctl_status           ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
--      ctl_status          =>  ctl_status           ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
 
 
--
 
      -- Fabric side: DLM Rx
 
--      -- Fabric side: DLM Rx
 
      dlm_tv              =>  dlm_tv               ,  -- OUT std_logic;
 
--      dlm_tv              =>  dlm_tv               ,  -- OUT std_logic;
 
      dlm_td              =>  dlm_td               ,  -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
--      dlm_td              =>  dlm_td               ,  -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
 
 
--
 
      -- Fabric side: DLM Tx
 
--      -- Fabric side: DLM Tx
 
      dlm_rv              =>  dlm_rv               ,  -- IN  std_logic;
 
--      dlm_rv              =>  dlm_rv               ,  -- IN  std_logic;
 
      dlm_rd              =>  dlm_rd               ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
--      dlm_rd              =>  dlm_rd               ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
 
 
 
 
      -- Event Buffer status + reset
 
      -- Event Buffer status + reset
 
      eb_FIFO_Status      =>  eb_FIFO_Status  ,      -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
      eb_FIFO_Status      =>  eb_FIFO_Status  ,      -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
      eb_FIFO_Rst         =>  eb_FIFO_Rst     ,      -- OUT std_logic;
 
      eb_FIFO_Rst         =>  eb_FIFO_Rst     ,      -- OUT std_logic;
 
 
 
 
Line 1380... Line 1380... 
      MRd_Channel_Rst     =>  MRd_Channel_Rst      ,  -- OUT std_logic;
 
      MRd_Channel_Rst     =>  MRd_Channel_Rst      ,  -- OUT std_logic;
 
      Tx_Reset            =>  Tx_Reset             ,  -- OUT std_logic;
 
      Tx_Reset            =>  Tx_Reset             ,  -- OUT std_logic;
 
 
 
 
 
      -- to Interrupt module
 
      -- to Interrupt module
 
      Sys_IRQ             =>  Sys_IRQ              ,  -- OUT std_logic_vector(31 downto 0);
 
      Sys_IRQ             =>  Sys_IRQ              ,  -- OUT std_logic_vector(31 downto 0);
 
      DAQ_irq             =>  DAQ_irq              ,  -- IN  std_logic;
 
--      DAQ_irq             =>  DAQ_irq              ,  -- IN  std_logic;
 
      CTL_irq             =>  CTL_irq              ,  -- IN  std_logic;
 
--      CTL_irq             =>  CTL_irq              ,  -- IN  std_logic;
 
      DLM_irq             =>  DLM_irq              ,  -- IN  std_logic;
 
--      DLM_irq             =>  DLM_irq              ,  -- IN  std_logic;
 
 
 
 
 
      -- System error and info
 
      -- System error and info
 
      eb_FIFO_ow          =>  eb_FIFO_ow           ,
 
      eb_FIFO_ow          =>  eb_FIFO_ow           ,
 
      Tx_TimeOut          =>  Tx_TimeOut           ,
 
      Tx_TimeOut          =>  Tx_TimeOut           ,
 
      Tx_eb_TimeOut       =>  Tx_eb_TimeOut        ,
 
      Tx_eb_TimeOut       =>  Tx_eb_TimeOut        ,
Line 1400... Line 1400... 
      IG_Latency          =>  IG_Latency           ,
 
      IG_Latency          =>  IG_Latency           ,
 
      IG_Num_Assert       =>  IG_Num_Assert        ,
 
      IG_Num_Assert       =>  IG_Num_Assert        ,
 
      IG_Num_Deassert     =>  IG_Num_Deassert      ,
 
      IG_Num_Deassert     =>  IG_Num_Deassert      ,
 
      IG_Asserting        =>  IG_Asserting         ,
 
      IG_Asserting        =>  IG_Asserting         ,
 
 
 
 
 
      -- Data generator control
 
--      -- Data generator control
 
      DG_is_Running       =>  DG_is_Running        ,
 
--      DG_is_Running       =>  DG_is_Running        ,
 
      DG_Reset            =>  DG_Reset             ,
 
--      DG_Reset            =>  DG_Reset             ,
 
      DG_Mask             =>  DG_Mask              ,
 
--      DG_Mask             =>  DG_Mask              ,
 
 
 
 
 
      -- Common 
      -- Common 
      trn_clk             =>  trn_clk              ,  -- IN  std_logic;
 
      trn_clk             =>  trn_clk              ,  -- IN  std_logic;
 
      trn_lnk_up_n        =>  trn_lnk_up_n         ,  -- IN  std_logic,
 
      trn_lnk_up_n        =>  trn_lnk_up_n         ,  -- IN  std_logic,
 
      trn_reset_n         =>  trn_reset_n             -- IN  std_logic;
 
      trn_reset_n         =>  trn_reset_n             -- IN  std_logic;

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