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// ===========================================================================
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// File : ti_phy_top.v
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// Author : cmagleby
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// Date : Mon Dec 3 11:03:46 MST 2007
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// Project : TI PHY design
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//
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// Copyright (c) notice
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// This code adheres to the GNU public license
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// Please contact www.gutzlogic.com for details.
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// cmagleby@gutzlogic.com; cwinward@gutzlogic.com
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//
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// ===========================================================================
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//
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// $Id: ti_phy_top.v,v 1.2 2008-01-15 03:25:07 cmagleby Exp $
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//
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// ===========================================================================
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2007/12/05 18:37:06 cmagleby
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// importing tb files
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//
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//
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// ===========================================================================
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// Function : This file is non-synthesizable rtl file to demonstrate TS1's.
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// Insert your own RTL design here. It has dummy signals for a sram if that
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// can be ignored.
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// ===========================================================================
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// ===========================================================================
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No newline at end of file
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No newline at end of file
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module ti_phy_top (/*AUTOARG*/
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// Outputs
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LED, txclk, txdata16, txdatak16, txidle16, rxdet_loopb, txcomp,
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rxpol, phy_reset_n, pwrdwn, sram_addr, sram_adscn, sram_adspn,
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sram_advn, sram_ben, sram_ce, sram_clk, sram_gwn, sram_mode,
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sram_oen, sram_wen, sram_zz,
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// Inouts
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sram_data,
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// Inputs
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clk_50mhz, PUSH_BUTTON, FPGA_RESET_n, PERST_n, rxclk, rxdata16,
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rxdatak16, rxvalid16, rxidle16, rxidle, rxstatus, phystatus
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);
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//****************************************************************************************
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//TI PHY interface
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//****************************************************************************************
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//debug ports
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input clk_50mhz;
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input [1:0] PUSH_BUTTON;
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output [7:0] LED;
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reg [7:0] LED;
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input FPGA_RESET_n;
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input PERST_n;
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//****************************************************************************************
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//Phillips PHY interface
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output txclk; //source synch 250 Mhz transmit clock from MAC.
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wire txclk;
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output [15:0] txdata16;
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reg [15:0] txdata16;
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output [1:0] txdatak16;
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reg [1:0] txdatak16;
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output txidle16; //forces tx output to electrical idle. txidle should be asserted while in power states p0 and p1.
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reg txidle16;
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input rxclk; //source synch 250 clk for received data.
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input [15:0] rxdata16;
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input [1:0] rxdatak16;
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input rxvalid16;
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output rxdet_loopb; //used to tell the phy to begin
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reg rxdet_loopb;
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input rxidle16;
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input rxidle; //indicates receiver detection of an electrical idle; This is a synchronous signal.
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input [2:0] rxstatus; //encodes receiver status and error codes.
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input phystatus; //used to communicate completion of several phy functions.
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output txcomp; //used when transmitting the compliance pattern; high-level sets the running disparity to negative.
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reg txcomp;
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output rxpol; //signals the phy to perform a polarity inversion on the receive data; low = no polarity inversion; high = polarity inversion.
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reg rxpol;
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output phy_reset_n; //phy reset active low
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reg phy_reset_n;
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output [1:0] pwrdwn;
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reg [1:0] pwrdwn;
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//****************************************************************************************
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//SRAM Interface
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output [16:0] sram_addr;
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reg [16:0] sram_addr;
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output sram_adscn;
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reg sram_adscn;
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output sram_adspn;
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reg sram_adspn;
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output sram_advn;
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reg sram_advn;
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output [3:0] sram_ben;
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reg [3:0] sram_ben;
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output [2:0] sram_ce;
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reg [2:0] sram_ce;
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output sram_clk;
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reg sram_clk;
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output sram_gwn;
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reg sram_gwn;
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output sram_mode;
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reg sram_mode;
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output sram_oen;
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reg sram_oen;
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output sram_wen;
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reg sram_wen;
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output sram_zz;
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reg sram_zz;
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inout [35:0] sram_data;
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assign txclk = rxclk;
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reg continue;
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initial begin
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LED <= 'b0;
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txdata16 <= 15'b0;
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txdatak16 <= 2'b0;
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txidle16 <= 1'b0;
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pwrdwn <= 2'b0;
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phy_reset_n <= 1'b0;
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rxpol <= 1'b0;
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txcomp <= 1'b0;
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rxdet_loopb <= 1'b0;
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phy_reset_n <= 1'b0;
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//ignore these signals
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sram_addr <= 'b0;
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sram_adscn <= 'b0;
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sram_adspn <= 'b0;
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sram_advn <= 'b0;
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sram_ben <= 'b0;
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sram_ce <= 'b0;
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sram_clk <= 'b0;
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sram_gwn <= 'b0;
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sram_mode <= 'b0;
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sram_oen <= 'b0;
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sram_wen <= 'b0;
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sram_zz <= 'b0;
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//sram_data <= 'b0;
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continue <= 1'b1;
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#100;
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phy_reset_n <= 1'b1;
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sample_ts1();
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end
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task sample_ts1;
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begin
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pwrdwn <= 2'b10;
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@ (negedge rxclk);
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wait (phystatus == 0); //indicate that the pll is locked.
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repeat (20) @ (negedge rxclk);
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rxdet_loopb <= 1'b1;
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wait (phystatus == 1'b1 && rxstatus == 3'b11); //receiver detect
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repeat (5) @ (negedge rxclk);
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rxdet_loopb <= 1'b0;
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repeat (2) @ (negedge rxclk);
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pwrdwn <= 2'b0;
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wait (phystatus == 1'b0);
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wait (phystatus == 1'b1 && rxstatus == 4'b100); //power change accept
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repeat (100) @ (negedge rxclk);
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while (continue == 1) begin
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//start sending ts1;
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@ (negedge rxclk);
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txdatak16 <= 2'b11;
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txdata16 <= 16'hf7bc; //PAD LINK,COM
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@ (negedge rxclk);
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txdatak16 <= 2'b01;
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txdata16 <= 16'hf0f7; //NFST,PAD LANE
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@ (negedge rxclk);
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txdatak16 <= 2'b0;
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txdata16 <= 16'h02; //training control Rate ID
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@ (negedge rxclk);
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txdatak16 <= 2'b0;
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txdata16 <= 16'h4a4a; //ts id
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@ (negedge rxclk);
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txdatak16 <= 2'b0;
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txdata16 <= 16'h4a4a; //ts id
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@ (negedge rxclk);
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txdatak16 <= 2'b0;
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txdata16 <= 16'h4a4a; //ts id
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@ (negedge rxclk);
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txdatak16 <= 2'b0;
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txdata16 <= 16'h4a4a; //ts id
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@ (negedge rxclk);
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txdatak16 <= 2'b0;
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txdata16 <= 16'h4a4a; //ts id
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//add sending ts2;
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//add link and lane
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end // while (continue == 1)
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end
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endtask // sample_ts1
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endmodule
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// Local Variables:
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// verilog-library-directories:("." "./dcm" "./ddr_div2" "./single_dcm" "./dll" "./tl")
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// End:
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