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// ===========================================================================
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// File : ti_phy_top.vr
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// Author : cmagleby
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// Date : Mon Dec 3 11:03:46 MST 2007
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// Project : TI PHY design
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//
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// Copyright (c) notice
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// This code adheres to the GNU public license
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// Please contact www.gutzlogic.com for details.
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// cmagleby@gutzlogic.com; cwinward@gutzlogic.com
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// ===========================================================================
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//
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// $Id: ti_phy_top.vr,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
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//
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// ===========================================================================
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//
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// $Log: not supported by cvs2svn $
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//
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// ===========================================================================
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// Function : This is the top level VERA file. It call all tasks and brings
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// up the PHY.
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// ===========================================================================
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// ===========================================================================
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#define OUTPUT_EDGE PHOLD
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#define OUTPUT_SKEW #1
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#define INPUT_SKEW #-1
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#define INPUT_EDGE PSAMPLE
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#include
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// define interfaces, and verilog_node here if necessary
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#include "ti_phy_top.if.vrh"
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#include "receive_packet.vri"
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#include "send_packet.vri"
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#include "pcie_phy_packet.vri"
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#include "link_training.vri"
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#include "skip_order_set.vri"
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#include "pcie_dllp_packet.vri"
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#include "InitFC1.vri"
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#include "pcie_tlp_packet.vri"
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#include "tlp_gen.vri"
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//kcode symbols
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#define COM_s 8'hbc
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#define SKP_s 8'h1c
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#define IDLE_s 8'h7c
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#define FTS_s 8'h3c
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#define STP_s 8'hfb
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#define SDP_s 8'h5c
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#define EDB 8'hfe
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#define END_s 8'hfd
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program ti_phy_top_test {
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pcie_phy_packet training_set;
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pcie_phy_packet skip_set;
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//********************************
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//link training gobal variables
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integer send_ts1 = 1;
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integer send_ts2 = 0;
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bit [11:0] sequence_id;
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bit [31:0] packet_array [1040];
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bit [7:0] link = 8'hf7;
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bit [7:0] lane = 8'hf7;
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integer ts1_cycle_cnt = 1;
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integer ts2_cycle_cnt = 1;
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integer LINK_UP = 0;
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bit [7:0] ph_cl = 8'b0;
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bit [11:0] pd_cl = 12'b0;
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bit [7:0] cplh_cl = 8'b0;
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bit [11:0] cpld_cl = 12'b0;
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bit [7:0] nph_cl = 8'b0;
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bit [11:0] npd_cl = 12'b0;
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bit INITFC_DONE = 1'b0;
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//********************************
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pcie_dllp_packet flowcntrl_1;
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pcie_dllp_packet ack_seq_num;
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pcie_tlp_packet tlp_packet;
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integer phy_rdy = 0;
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integer my_semaphore;
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bit [8:0] tx_data_mailbox;
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bit [15:0] tlp_header_mailbox;
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bit [31:0] tlp_data_mailbox;
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bit [47:0] dllp_mailbox;
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bit [127:0] phy_mailbox;
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bit [17:0] rx_data_mailbox;
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//create mailboxes for transmit and receive packets
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tx_data_mailbox = alloc(MAILBOX,0,1);
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rx_data_mailbox = alloc(MAILBOX,0,1);
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tlp_header_mailbox = alloc(MAILBOX,0,1);
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tlp_data_mailbox = alloc(MAILBOX,0,1);
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dllp_mailbox = alloc(MAILBOX,0,1);
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phy_mailbox = alloc(MAILBOX,0,1);
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//create a packet arbiter for packet going out on the rx line.
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my_semaphore = alloc(SEMAPHORE, 0, 1, 1);
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if (!my_semaphore) error ("Semaphore could not be allocated\n");
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fork
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clk_50mhz_gen();
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phy_status();
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skip_order_set();
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receive_packet();
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send_packet();
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wait_var(phy_rdy);
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link_training();
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join none
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init_ports ();
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reset_sequence();
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wait_var(LINK_UP);
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fork
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zero_fill();
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join none
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InitFC1(ph_cl,pd_cl,cplh_cl,cpld_cl,nph_cl,npd_cl,INITFC_DONE);
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printf("Posted Header credit %h\n",ph_cl);
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printf("Posted Data credit %h\n",pd_cl);
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printf("NonPosted Header credit %h\n",nph_cl);
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printf("NonPosted Data credit %h\n",npd_cl);
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printf("Completion Header credit %h\n",cplh_cl);
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printf("Completion Data credit %h\n",cpld_cl);
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printf("INITFC_DONE=%d\n.",INITFC_DONE);
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tlp_gen();
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repeat (10000) @(posedge CLOCK);
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} // end of program ti_phy_top_test
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// define tasks/classes/functions here if necessary
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task clk_50mhz_gen () {
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ti_phy_top.clk_50mhz = 0;
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@(posedge ti_phy_top.rxclk);
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while(1) {
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@10 ti_phy_top.clk_50mhz = 1;
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@10 ti_phy_top.clk_50mhz = 0;
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}
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}
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task init_ports () {
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printf("Task init_ports\n");
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@(posedge ti_phy_top.rxclk);
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ti_phy_top.FPGA_RESET_n = 1'b0;
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ti_phy_top.rxdata16 = 16'b0;
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ti_phy_top.rxdatak16 = 2'b0;
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ti_phy_top.rxvalid16 = 1'b0;
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ti_phy_top.rxidle16 = 1'b0;
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ti_phy_top.rxstatus = 1'b1;
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ti_phy_top.phystatus = 1'b1;
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}
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task reset_sequence() {
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printf("Task phy bring up\n");
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@5 ti_phy_top.FPGA_RESET_n = 1'b0;
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@1 ti_phy_top.FPGA_RESET_n = 1'b1;
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}
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task phy_status () {
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bit [1:0] prev_pwrdwn = 0;
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integer loop_back_high;
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integer phy_status_arb;
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phy_status_arb = alloc(SEMAPHORE,0,1,1);
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if (!phy_status_arb) error ("Semaphore could not be allocated\n");
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printf("Look for power changes\n");
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@50 ti_phy_top.rxidle16 = 1'b0;
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@100 ti_phy_top.phystatus = 1'b0;
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while (1){
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prev_pwrdwn = ti_phy_top.pwrdwn;
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@(posedge CLOCK);
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//receiver detect
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if (ti_phy_top.rxdet_loopb == 1'b1 && ti_phy_top.pwrdwn == 2'b10) {
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loop_back_high = 1;
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if (!semaphore_get(WAIT,phy_status_arb,1))
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error ("Semaphore_get returned 0\n");
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//printf("GOT PHY ARB1 /n");
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@10 ti_phy_top.rxstatus = 3'b11;
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@10 ti_phy_top.phystatus = 1'b1;
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while(loop_back_high) {
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@(posedge CLOCK);
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if (ti_phy_top.rxdet_loopb == 1'b0) {
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loop_back_high = 1'b0;
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}
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}
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@4 ti_phy_top.phystatus = 1'b0;
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ti_phy_top.rxstatus = 3'b0;
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semaphore_put (phy_status_arb, 1);
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}
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if (ti_phy_top.pwrdwn != prev_pwrdwn){
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if (!semaphore_get(WAIT,phy_status_arb,1))
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error ("Semaphore_get returned 0\n");
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//printf("GOT PHY ARB2 /n");
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@1 ti_phy_top.rxstatus = 3'b100;
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ti_phy_top.phystatus = 1'b1;
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@1 ti_phy_top.phystatus = 1'b0;
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if (ti_phy_top.pwrdwn == 2'b00) phy_rdy = 1;
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semaphore_put (phy_status_arb, 1);
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}
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}
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}
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