| Line 23... |
Line 23... |
|
|
entity debounce is
|
entity debounce is
|
Port ( clk : in STD_LOGIC;
|
Port ( clk : in STD_LOGIC;
|
clken : in STD_LOGIC;
|
clken : in STD_LOGIC;
|
input : in STD_LOGIC;
|
input : in STD_LOGIC;
|
output : inout STD_LOGIC);
|
output : out STD_LOGIC);
|
end debounce;
|
end debounce;
|
|
|
-- Concept: input values are asynchronously connected to SR latches.
|
-- Concept: input values are asynchronously connected to SR latches.
|
-- Those are synchronously reset, so if both are set, the input is unstable.
|
-- Those are synchronously reset, so if both are set, the input is unstable.
|
-- On Spartan 3 FPGAs, this architecture probably requires at least three slices,
|
-- On Spartan 3 FPGAs, this architecture probably requires at least three slices,
|
-- due to separate RS lines for flip-flops. The output register may share, though.
|
-- due to separate RS lines for flip-flops. The output register may share, though.
|
architecture Behavioral of debounce is
|
architecture Behavioral of debounce is
|
-- 00->no input value observed (reset), 10 or 01 -> steady value, 11->value changed
|
-- 00->no input value observed (reset), 10 or 01 -> steady value, 11->value changed
|
signal inputv : std_logic_vector(0 to 1) := "00";
|
signal inputv : std_logic_vector(0 to 1) := "00";
|
signal next_output : std_logic;
|
signal next_output : std_logic;
|
|
signal current_output : std_logic;
|
begin
|
begin
|
|
output <= current_output;
|
-- our two asynch latches must agree for an update to occur
|
-- our two asynch latches must agree for an update to occur
|
-- the tricky part of the code was convincing the synthesizer we only need one LUT3
|
-- the tricky part of the code was convincing the synthesizer we only need one LUT3
|
-- to implement this consensus function (inputv must agree to alter output).
|
-- to implement this consensus function (inputv must agree to alter output).
|
with inputv select
|
with inputv select
|
next_output <= '0' when "10",
|
next_output <= '0' when "10",
|
'1' when "01",
|
'1' when "01",
|
output when others;
|
current_output when others;
|
process (clk, input)
|
process (clk, input)
|
begin
|
begin
|
-- input='0' for asynch set of input(0), synch reset
|
-- input='0' for asynch set of input(0), synch reset
|
if input='0' then
|
if input='0' then
|
inputv(0) <= '1';
|
inputv(0) <= '1';
|
| Line 58... |
Line 60... |
elsif clken='1' and rising_edge(clk) then
|
elsif clken='1' and rising_edge(clk) then
|
inputv(1) <= '0';
|
inputv(1) <= '0';
|
end if;
|
end if;
|
-- finally, on enabled clocks, update output
|
-- finally, on enabled clocks, update output
|
if clken='1' and rising_edge(clk) then
|
if clken='1' and rising_edge(clk) then
|
output <= next_output;
|
current_output <= next_output;
|
end if;
|
end if;
|
end process;
|
end process;
|
end Behavioral;
|
end Behavioral;
|
|
|
No newline at end of file
|
No newline at end of file
|
