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[/] [pdp1/] [trunk/] [rtl/] [vhdl/] [pdp1cpu.vhd] - Diff between revs 3 and 9

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Rev 3 Rev 9
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--   PDP-1C had full multiply and divide instructions of variable time.
--   PDP-1C had full multiply and divide instructions of variable time.
--
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Why does isim behave like unsigned+natural doesn't exist?
use IEEE.NUMERIC_STD.ALL;
use IEEE.NUMERIC_STD.ALL;
 
 
 
 
entity pdp1cpu is
entity pdp1cpu is
    Port (
    Port (
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      AWAKE : out STD_LOGIC;
      AWAKE : out STD_LOGIC;
 
 
      -- user visible registers
      -- user visible registers
      AC : inout STD_LOGIC_VECTOR(0 to 17)       := (others=>'0');  -- accumulator
      AC : inout STD_LOGIC_VECTOR(0 to 17)       := (others=>'0');  -- accumulator
      IO : inout STD_LOGIC_VECTOR(0 to 17)       := (others=>'0');  -- I/O
      IO : inout STD_LOGIC_VECTOR(0 to 17)       := (others=>'0');  -- I/O
      PC : inout unsigned(0 to 11)       := (others=>'0');  -- program counter
      PC : inout STD_LOGIC_VECTOR(0 to 11)       := (others=>'0');  -- program counter
      PF : inout STD_LOGIC_VECTOR(1 to 6)       := (others=>'0');  -- program flags
      PF : inout STD_LOGIC_VECTOR(1 to 6)       := (others=>'0');  -- program flags
      OV : inout STD_LOGIC := '0';      -- overflow flag
      OV : inout STD_LOGIC := '0';      -- overflow flag
 
 
      -- user settable switches
      -- user settable switches
      SW_TESTA : in std_logic_vector(0 to 11) := (others => '0');  -- test address
      SW_TESTA : in std_logic_vector(0 to 11) := (others => '0');  -- test address
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                  MB <= M_DO;
                  MB <= M_DO;
                  case cycletype is
                  case cycletype is
                    when load_instruction =>    -- it's our next instruction
                    when load_instruction =>    -- it's our next instruction
                      op <= M_DO(0 to 5);
                      op <= M_DO(0 to 5);
                      if op/=op_xct then  -- indirect execution
                      if op/=op_xct then  -- indirect execution
                        PC<=PC+1;
                        PC<=std_logic_vector(unsigned(PC)+1);
                      end if;
                      end if;
                    when load_indirect =>               -- completing an indirect instruction
                    when load_indirect =>               -- completing an indirect instruction
                      ib <= M_DO(5);            -- update indirection bit
                      ib <= M_DO(5);            -- update indirection bit
                    when others =>              -- data access cycle
                    when others =>              -- data access cycle
                  end case;
                  end case;
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                  if ((op=op_skip or op=op_skipi) and (skipcond xor ib)='1') or
                  if ((op=op_skip or op=op_skipi) and (skipcond xor ib)='1') or
                     (op=op_isp and cycletype=store_data and AC(0)='0') or
                     (op=op_isp and cycletype=store_data and AC(0)='0') or
                     (op=op_sas and cycletype=load_data and ac_eq_mb) or
                     (op=op_sas and cycletype=load_data and ac_eq_mb) or
                     (op=op_sad and cycletype=load_data and not ac_eq_mb) or
                     (op=op_sad and cycletype=load_data and not ac_eq_mb) or
                     FALSE then    -- increase PC an extra time
                     FALSE then    -- increase PC an extra time
                    PC <= PC+1;
                    PC <= std_logic_vector(unsigned(PC)+1);
                  end if;
                  end if;
                  if (op=op_skip or op=op_skipi) and szo='1' then
                  if (op=op_skip or op=op_skipi) and szo='1' then
                    OV <= '0';          -- clear overflow after checking it
                    OV <= '0';          -- clear overflow after checking it
                  end if;
                  end if;
                when cycle_setup_read =>        -- set up the memory address
                when cycle_setup_read =>        -- set up the memory address
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                          if op=op_cal or op=op_jda then
                          if op=op_cal or op=op_jda then
                            if op=op_cal then
                            if op=op_cal then
                              PC <= o"0101";
                              PC <= o"0101";
                              MA <= o"0100";
                              MA <= o"0100";
                            else
                            else
                              PC <= unsigned(y)+1;
                              PC <= std_logic_vector(unsigned(y)+1);
                              MA <= y;
                              MA <= y;
                            end if;
                            end if;
                            cycletype <= store_data;
                            cycletype <= store_data;
                          else
                          else
                            MA <= y;
                            MA <= y;
                            PC <= unsigned(y);
                            PC <= y;
                            cycletype <= load_instruction;
                            cycletype <= load_instruction;
                          end if;
                          end if;
                        when op_skipi|op_rotshiftr|op_lawm|op_iot_nw =>
                        when op_skipi|op_rotshiftr|op_lawm|op_iot_nw =>
                          -- instructions with IB set, yet are immediate
                          -- instructions with IB set, yet are immediate
                          MA <= std_logic_vector(PC);
                          MA <= std_logic_vector(PC);

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